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/freebsd/sys/contrib/device-tree/Bindings/gpu/
H A Dapple,agx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sasha Finkelstein <fnkl.kernel@gmail.com>
15 - enum:
16 - apple,agx-g13g
17 - apple,agx-g13s
18 - apple,agx-g14g
19 - items:
20 - enum:
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416_cal.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
27 #include "ar5212/ar5212.h" /* for NF cal related declarations */
61 * Analog-to-Digital Converters."
67 struct ar5416PerCal *cal = &AH5416(ah)->ah_cal; in ar5416IsCalSupp() local
69 switch (calType & cal->suppCals) { in ar5416IsCalSupp()
71 /* Run IQ Mismatch for non-CCK only */ in ar5416IsCalSupp()
76 * Run ADC Gain Cal for either 5ghz any or 2ghz HT40. in ar5416IsCalSupp()
[all …]
/freebsd/sys/dev/malo/
H A Dif_malohal.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * redistribution must be conditioned upon including a substantially
24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
59 pCmd = (_type *)&mh->mh_cmdbuf[0]; \
61 pCmd->cmdhdr.cmd = htole16(_cmd); \
62 pCmd->cmdhdr.length = htole16(sizeof(_type)); \
68 return bus_space_read_4(mh->mh_iot, mh->mh_ioh, off); in malo_hal_read4()
74 bus_space_write_4(mh->mh_iot, mh->mh_ioh, off, val); in malo_hal_write4()
[all …]
H A Dif_malohal.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * redistribution must be conditioned upon including a substantially
24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
48 * has a single set of calibration tables that we retrieve right
50 * a different regdomain and/or tx power setup).
62 uint8_t hwversion; /* version of the HW */
68 /* MAC address programmed in HW */
81 * Supply tx/rx dma-related settings to the firmware.
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c121 ahp->ah_hwp = HAL_TRUE_CHIP; in ar9300_attach_hw_platform()
189 HALDEBUG(ah, HAL_DEBUG_RESET, "%s using HW crypto\n", __func__); in ar9300_init_mfp()
196 * Mask used to construct AAD for CCMP-AES in ar9300_init_mfp()
197 * Cisco spec defined bits 0-3 as mask in ar9300_init_mfp()
226 centers->ctl_center = centers->ext_center = in ar9300_get_channel_centers()
227 centers->synth_center = ichan->channel; in ar9300_get_channel_centers()
238 centers->synth_center = ichan->channel + HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()
241 centers->synth_center = ichan->channel - HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()
242 extoff = -1; in ar9300_get_channel_centers()
245 centers->ctl_center = in ar9300_get_channel_centers()
[all …]
H A Dar9300_spectral.c199 if (AH_PRIVATE(ah)->ah_curchan && in ar9300_prep_spectral_scan()
200 IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan)) in ar9300_prep_spectral_scan()
218 int cal; member
228 /* ch 1 */ {2412, { {N2DBM(-101, 00), N2DBM( -94, 25)},
229 {N2DBM(-107, 75), N2DBM( -99, 75)},
231 /* ch 6 */ {2437, { {N2DBM(-102, 25), N2DBM( -94, 25)},
232 {N2DBM(-106, 00), N2DBM( -97, 25)},
234 /* ch 11 */ {2462, { {N2DBM(-101, 50), N2DBM( -95, 00)},
235 {N2DBM(-105, 50), N2DBM( -98, 00)},
237 /* ch 36 */ {5180, { {N2DBM(-114, 25), N2DBM( -95, 00)},
[all …]
H A Dar9300.h31 * (a) this should be N(a),
35 #define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0])) argument
48 #define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */
51 * Various fifo fill before Tx start, in 64-byte units
55 #define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1)
151 * Per-channel ANI state private to the driver.
178 u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */
195 ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI))
211 u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
288 #define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ti/
H A Demif.txt3 EMIF - External Memory Interface - is an SDRAM controller used in
5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
24 - device-handle : phandle to a "lpddr2" node representing the memory part
26 - ti,hwmods : For TI hwmods processing and omap device creation
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
[all …]
H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
23 const: nvidia,tegra30-emc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dqcom,ath10k.txt4 - compatible: Should be one of the following:
6 * "qcom,ipq4019-wifi"
7 * "qcom,wcn3990-wifi"
10 data along with board specific data via "qcom,ath10k-calibration-data".
13 AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
15 "qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
18 In general, entry "qcom,ath10k-pre-calibration-data" and
19 "qcom,ath10k-calibration-data" conflict with each other and only one
22 SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".
24 - reg: Address and length of the register set for the device.
[all …]
/freebsd/sys/arm/nvidia/
H A Dtegra_soctherm.c1 /*-
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
52 #include <dt-bindings/thermal/tegra124-soctherm.h>
55 /* Per sensors registers - base is 0x0c0*/
131 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
132 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
208 .fuse_corr_beta = -6266900,
212 .id = -1,
216 .fuse_corr_beta = -5700700,
220 .id = -1,
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_util.c1 // SPDX-License-Identifier: ISC
92 struct mt76x02_dev *dev = container_of(mphy->dev, struct mt76x02_dev, in mt76x02_led_set_config()
100 mt76_wr(dev, MT_LED_S0(mphy->leds.pin), val); in mt76x02_led_set_config()
101 mt76_wr(dev, MT_LED_S1(mphy->leds.pin), val); in mt76x02_led_set_config()
103 val = MT_LED_CTRL_REPLAY(mphy->leds.pin) | in mt76x02_led_set_config()
104 MT_LED_CTRL_KICK(mphy->leds.pin); in mt76x02_led_set_config()
105 if (mphy->leds.al) in mt76x02_led_set_config()
106 val |= MT_LED_CTRL_POLARITY(mphy->leds.pin); in mt76x02_led_set_config()
142 struct ieee80211_hw *hw = mt76_hw(dev); in mt76x02_init_device() local
143 struct wiphy *wiphy = hw->wiphy; in mt76x02_init_device()
[all …]
H A Dmt76x02_mac.c1 // SPDX-License-Identifier: ISC
28 memset(dev->mphy.aggr_stats, 0, sizeof(dev->mphy.aggr_stats)); in mt76x02_mac_reset_counters()
39 if (key->keylen > 32) in mt76x02_mac_get_key_info()
42 memcpy(key_data, key->key, key->keylen); in mt76x02_mac_get_key_info()
44 switch (key->cipher) { in mt76x02_mac_get_key_info()
67 return -EOPNOTSUPP; in mt76x02_mac_shared_key_setup()
103 atomic64_set(&key->tx_pn, pn); in mt76x02_mac_wcid_sync_pn()
116 return -EOPNOTSUPP; in mt76x02_mac_wcid_set_key()
124 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); in mt76x02_mac_wcid_set_key()
126 pn = atomic64_read(&key->tx_pn); in mt76x02_mac_wcid_set_key()
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatop.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * kitchen-sinked this device, not us. :)
39 * them, we just export a couple public functions to allow the imx6 CCM clock
46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes
52 * are deci-Celsius, which are converted to/from deci-Kelvins in the sysctl
81 { -1, 0 }
136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
141 #define TZ_ZEROC 2731 /* deci-Kelvin <-> deci-Celsius offset. */
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dcore.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
21 #include <linux/nvmem-consumer.h>
33 #include "wmi-ops.h"
65 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
473 * or 2x2 160Mhz, long-guard-interval.
523 * 1x1 160Mhz, long-guard-interval.
741 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
[all …]
H A Dcore.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
20 #include "hw.h"
49 #define ATH10K_DEFAULT_NOISE_FLOOR -95
70 /* SMBIOS type structure length (excluding strings-set) */
145 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; in ATH10K_SKB_CB()
150 BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb)); in ATH10K_SKB_RXCB()
151 return (struct ath10k_skb_rxcb *)skb->cb; in ATH10K_SKB_RXCB()
[all …]
/freebsd/sys/dev/mwl/
H A Dmwlhal.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16 * redistribution must be conditioned upon including a substantially
23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
78 * BA stream -> queue ID mapping
98 pCmd = (type *)&mh->mh_cmdbuf[0]; \
100 pCmd->CmdHdr.Cmd = htole16(cmd); \
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0>; /* To be filled by loader */
69 next-level-cache = <&l2_cache_0>;
70 i-cache-size = <0x20000>;
[all …]
H A Dt8103.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8103", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
27 #address-cells = <2>;
[all …]
H A Dt8112.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
27 #address-cells = <2>;
[all …]
H A Dt600x-die0.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
24 power-domains = <&ps_aic>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dmcu.c1 // SPDX-License-Identifier: ISC
12 switch (mt76_chip(&(_dev)->mt76)) { \
47 for (nss = 8; nss > 0; nss--) { in mt7915_mcu_get_sta_nss()
48 u8 nss_mcs = (mcs_map >> (2 * (nss - 1))) & 3; in mt7915_mcu_get_sta_nss()
54 return nss - 1; in mt7915_mcu_get_sta_nss()
61 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; in mt7915_mcu_set_sta_he_mcs()
62 struct mt7915_dev *dev = msta->vif->phy->dev; in mt7915_mcu_set_sta_he_mcs()
63 enum nl80211_band band = msta->vif->phy->mt76->chandef.chan->band; in mt7915_mcu_set_sta_he_mcs()
64 const u16 *mask = msta->vif->bitrate_mask.control[band].he_mcs; in mt7915_mcu_set_sta_he_mcs()
65 int nss, max_nss = sta->deflink.rx_nss > 3 ? 4 : sta->deflink.rx_nss; in mt7915_mcu_set_sta_he_mcs()
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210_reset.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
47 * The delay, in usecs, between writing AR_RC with a reset
51 * on the host machine (don't know--the problem was identified
67 * a HW Reset during channel change.
75 #define N(a) (sizeof (a) /sizeof (a[0])) in ar5210Reset() argument
78 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; in ar5210Reset()
86 opmode, chan->ic_freq, chan->ic_flags, in ar5210Reset()
[all …]
/freebsd/usr.bin/fortune/datfiles/
H A Dfreebsd-tips1 Any user that is a member of the wheel group can use "su -" to simulate
2 a root login. You can add a user to the wheel group with:
3 pw groupmod -n wheel -m user_name
4 -- Konstantinos Konstantinidis <kkonstan@duth.gr>
8 Don't have a "Scroll Lock" key? The "Pause / Break" key acts alike.
10 Can't remember if you've installed a certain port or not? Try "pkg info
11 -x port_name".
15 -- David Scheidt <dscheidt@tumbolia.com>
17 Forget how to spell a word or a variation of a word? Use
20 -- Dru <genesis@istar.ca>
[all …]

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