xref: /freebsd/sys/dev/malo/if_malohal.h (revision 95ee2897e98f5d444f26ed2334cc7c439f9c16c6)
13c7e78d3SWeongyo Jeong /*-
2*4d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
3718cf2ccSPedro F. Giffuni  *
43c7e78d3SWeongyo Jeong  * Copyright (c) 2007 Marvell Semiconductor, Inc.
53c7e78d3SWeongyo Jeong  * Copyright (c) 2007 Sam Leffler, Errno Consulting
63c7e78d3SWeongyo Jeong  * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org>
73c7e78d3SWeongyo Jeong  * All rights reserved.
83c7e78d3SWeongyo Jeong  *
93c7e78d3SWeongyo Jeong  * Redistribution and use in source and binary forms, with or without
103c7e78d3SWeongyo Jeong  * modification, are permitted provided that the following conditions
113c7e78d3SWeongyo Jeong  * are met:
123c7e78d3SWeongyo Jeong  * 1. Redistributions of source code must retain the above copyright
133c7e78d3SWeongyo Jeong  *    notice, this list of conditions and the following disclaimer,
143c7e78d3SWeongyo Jeong  *    without modification.
153c7e78d3SWeongyo Jeong  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
163c7e78d3SWeongyo Jeong  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
173c7e78d3SWeongyo Jeong  *    redistribution must be conditioned upon including a substantially
183c7e78d3SWeongyo Jeong  *    similar Disclaimer requirement for further binary redistribution.
193c7e78d3SWeongyo Jeong  *
203c7e78d3SWeongyo Jeong  * NO WARRANTY
213c7e78d3SWeongyo Jeong  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
223c7e78d3SWeongyo Jeong  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
233c7e78d3SWeongyo Jeong  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
243c7e78d3SWeongyo Jeong  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
253c7e78d3SWeongyo Jeong  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
263c7e78d3SWeongyo Jeong  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
273c7e78d3SWeongyo Jeong  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
283c7e78d3SWeongyo Jeong  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
293c7e78d3SWeongyo Jeong  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
303c7e78d3SWeongyo Jeong  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
313c7e78d3SWeongyo Jeong  * THE POSSIBILITY OF SUCH DAMAGES.
323c7e78d3SWeongyo Jeong  */
333c7e78d3SWeongyo Jeong 
343c7e78d3SWeongyo Jeong #ifndef _DEV_MALOHAL_H
353c7e78d3SWeongyo Jeong #define _DEV_MALOHAL_H
363c7e78d3SWeongyo Jeong 
373c7e78d3SWeongyo Jeong #define MALO_NUM_TX_QUEUES			1
383c7e78d3SWeongyo Jeong #define MALO_MAX_TXWCB_QUEUES			MALO_NUM_TX_QUEUES
393c7e78d3SWeongyo Jeong 
403c7e78d3SWeongyo Jeong /* size of f/w command buffer */
413c7e78d3SWeongyo Jeong #define	MALO_CMDBUF_SIZE			0x4000
423c7e78d3SWeongyo Jeong 
433c7e78d3SWeongyo Jeong #define MALO_FW_CHECK_USECS			(5 * 1000)	/* 5ms */
443c7e78d3SWeongyo Jeong #define MALO_FW_MAX_NUM_CHECKS			200
453c7e78d3SWeongyo Jeong 
463c7e78d3SWeongyo Jeong /*
473c7e78d3SWeongyo Jeong  * Calibration data builtin to the firmware.  The firmware image
483c7e78d3SWeongyo Jeong  * has a single set of calibration tables that we retrieve right
49b55a0762SGordon Bergling  * after download.  This can be overridden by the driver (e.g. for
503c7e78d3SWeongyo Jeong  * a different regdomain and/or tx power setup).
513c7e78d3SWeongyo Jeong  */
523c7e78d3SWeongyo Jeong struct malo_hal_caldata {
533c7e78d3SWeongyo Jeong 	/* pt is short for `power target'.  */
543c7e78d3SWeongyo Jeong #define	MALO_PWTAGETRATETABLE20M		(14 * 4)
553c7e78d3SWeongyo Jeong 	uint8_t	pt_ratetable_20m[MALO_PWTAGETRATETABLE20M];
563c7e78d3SWeongyo Jeong };
573c7e78d3SWeongyo Jeong 
583c7e78d3SWeongyo Jeong /*
593c7e78d3SWeongyo Jeong  * Get Hardware/Firmware capabilities.
603c7e78d3SWeongyo Jeong  */
613c7e78d3SWeongyo Jeong struct malo_hal_hwspec {
623c7e78d3SWeongyo Jeong 	uint8_t		hwversion;		/* version of the HW */
633c7e78d3SWeongyo Jeong 	uint8_t		hostinterface;	/* host interface */
643c7e78d3SWeongyo Jeong 	uint16_t	maxnum_wcb;		/* max # of WCB FW handles */
653c7e78d3SWeongyo Jeong 	/* max # of mcast addresses FW handles*/
663c7e78d3SWeongyo Jeong 	uint16_t	maxnum_mcaddr;
673c7e78d3SWeongyo Jeong 	uint16_t	maxnum_tx_wcb;	/* max # of tx descs per WCB */
683c7e78d3SWeongyo Jeong 	/* MAC address programmed in HW */
693c7e78d3SWeongyo Jeong 	uint8_t		macaddr[6];
703c7e78d3SWeongyo Jeong 	uint16_t	regioncode;		/* EEPROM region code */
713c7e78d3SWeongyo Jeong 	uint16_t	num_antenna;	/* Number of antenna used */
723c7e78d3SWeongyo Jeong 	uint32_t	fw_releasenum;	/* firmware release number */
733c7e78d3SWeongyo Jeong 	uint32_t	wcbbase0;
743c7e78d3SWeongyo Jeong 	uint32_t	rxdesc_read;
753c7e78d3SWeongyo Jeong 	uint32_t	rxdesc_write;
763c7e78d3SWeongyo Jeong 	uint32_t	ul_fw_awakecookie;
773c7e78d3SWeongyo Jeong 	uint32_t	wcbbase[4];
783c7e78d3SWeongyo Jeong };
793c7e78d3SWeongyo Jeong 
803c7e78d3SWeongyo Jeong /*
813c7e78d3SWeongyo Jeong  * Supply tx/rx dma-related settings to the firmware.
823c7e78d3SWeongyo Jeong  */
833c7e78d3SWeongyo Jeong struct malo_hal_txrxdma {
843c7e78d3SWeongyo Jeong 	uint32_t	maxnum_wcb;		/* max # of WCB FW handles */
853c7e78d3SWeongyo Jeong 	uint32_t	maxnum_txwcb;		/* max # of tx descs per WCB */
863c7e78d3SWeongyo Jeong 	uint32_t	rxdesc_read;
873c7e78d3SWeongyo Jeong 	uint32_t	rxdesc_write;
883c7e78d3SWeongyo Jeong 	uint32_t	wcbbase[4];
893c7e78d3SWeongyo Jeong };
903c7e78d3SWeongyo Jeong 
913c7e78d3SWeongyo Jeong /*
923c7e78d3SWeongyo Jeong  * Get Hardware Statistics.
933c7e78d3SWeongyo Jeong  *
943c7e78d3SWeongyo Jeong  * Items marked with ! are deprecated and not ever updated.  In
953c7e78d3SWeongyo Jeong  * some cases this is because work has been moved to the host (e.g.
963c7e78d3SWeongyo Jeong  * rx defragmentation).
973c7e78d3SWeongyo Jeong  *
983c7e78d3SWeongyo Jeong  * XXX low/up cases.
993c7e78d3SWeongyo Jeong  */
1003c7e78d3SWeongyo Jeong struct malo_hal_hwstats {
1013c7e78d3SWeongyo Jeong 	uint32_t	TxRetrySuccesses;	/* tx success w/ 1 retry */
1023c7e78d3SWeongyo Jeong 	uint32_t	TxMultipleRetrySuccesses;/* tx success w/ >1 retry */
1033c7e78d3SWeongyo Jeong 	uint32_t	TxFailures;		/* tx fail due to no ACK */
1043c7e78d3SWeongyo Jeong 	uint32_t	RTSSuccesses;		/* CTS rx'd for RTS */
1053c7e78d3SWeongyo Jeong 	uint32_t	RTSFailures;		/* CTS not rx'd for RTS */
1063c7e78d3SWeongyo Jeong 	uint32_t	AckFailures;		/* same as TxFailures */
1073c7e78d3SWeongyo Jeong 	uint32_t	RxDuplicateFrames;	/* rx discard for dup seqno */
1083c7e78d3SWeongyo Jeong 	uint32_t	FCSErrorCount;		/* rx discard for bad FCS */
1093c7e78d3SWeongyo Jeong 	uint32_t	TxWatchDogTimeouts;	/* MAC tx hang (f/w recovery) */
1103c7e78d3SWeongyo Jeong 	uint32_t	RxOverflows;		/* no f/w buffer for rx data */
1113c7e78d3SWeongyo Jeong 	uint32_t	RxFragErrors;		/* !rx fail due to defrag */
1123c7e78d3SWeongyo Jeong 	uint32_t	RxMemErrors;		/* out of mem or desc corrupted
1133c7e78d3SWeongyo Jeong 						   in some way */
1143c7e78d3SWeongyo Jeong 	uint32_t	RxPointerErrors;	/* MAC internal ptr problem */
1153c7e78d3SWeongyo Jeong 	uint32_t	TxUnderflows;		/* !tx underflow on dma */
1163c7e78d3SWeongyo Jeong 	uint32_t	TxDone;			/* MAC tx ops completed
1173c7e78d3SWeongyo Jeong 						   (possibly w/ error) */
1183c7e78d3SWeongyo Jeong 	uint32_t	TxDoneBufTryPut;	/* ! */
1193c7e78d3SWeongyo Jeong 	uint32_t	TxDoneBufPut;		/* same as TxDone */
1203c7e78d3SWeongyo Jeong 	uint32_t	Wait4TxBuf;		/* !no f/w buf avail when
1213c7e78d3SWeongyo Jeong 						    supplied a tx descriptor */
1223c7e78d3SWeongyo Jeong 	uint32_t	TxAttempts;		/* tx descriptors processed */
1233c7e78d3SWeongyo Jeong 	uint32_t	TxSuccesses;		/* tx attempts successful */
1243c7e78d3SWeongyo Jeong 	uint32_t	TxFragments;		/* tx with fragmentation */
1253c7e78d3SWeongyo Jeong 	uint32_t	TxMulticasts;		/* tx multicast frames */
1263c7e78d3SWeongyo Jeong 	uint32_t	RxNonCtlPkts;		/* rx non-control frames */
1273c7e78d3SWeongyo Jeong 	uint32_t	RxMulticasts;		/* rx multicast frames */
1283c7e78d3SWeongyo Jeong 	uint32_t	RxUndecryptableFrames;	/* rx failed due to crypto */
1293c7e78d3SWeongyo Jeong 	uint32_t 	RxICVErrors;		/* rx failed due to ICV check */
1303c7e78d3SWeongyo Jeong 	uint32_t	RxExcludedFrames;	/* rx discarded, e.g. bssid */
1313c7e78d3SWeongyo Jeong };
1323c7e78d3SWeongyo Jeong 
1333c7e78d3SWeongyo Jeong /*
1343c7e78d3SWeongyo Jeong  * Set Antenna Configuration (legacy operation).
1353c7e78d3SWeongyo Jeong  *
1366bccea7cSRebecca Cran  * The RX antenna can be selected using the bitmask
1373c7e78d3SWeongyo Jeong  * ant (bit 0 = antenna 1, bit 1 = antenna 2, etc.)
1383c7e78d3SWeongyo Jeong  * (diversity?XXX)
1393c7e78d3SWeongyo Jeong  */
1403c7e78d3SWeongyo Jeong enum malo_hal_antenna {
1413c7e78d3SWeongyo Jeong 	MHA_ANTENNATYPE_RX	= 1,
1423c7e78d3SWeongyo Jeong 	MHA_ANTENNATYPE_TX	= 2,
1433c7e78d3SWeongyo Jeong };
1443c7e78d3SWeongyo Jeong 
1453c7e78d3SWeongyo Jeong /*
1463c7e78d3SWeongyo Jeong  * Set Radio Configuration.
1473c7e78d3SWeongyo Jeong  *
1483c7e78d3SWeongyo Jeong  * onoff != 0 turns radio on; otherwise off.
1493c7e78d3SWeongyo Jeong  * if radio is enabled, the preamble is set too.
1503c7e78d3SWeongyo Jeong  */
1513c7e78d3SWeongyo Jeong enum malo_hal_preamble {
1523c7e78d3SWeongyo Jeong 	MHP_LONG_PREAMBLE	= 1,
1533c7e78d3SWeongyo Jeong 	MHP_SHORT_PREAMBLE	= 3,
1543c7e78d3SWeongyo Jeong 	MHP_AUTO_PREAMBLE	= 5,
1553c7e78d3SWeongyo Jeong };
1563c7e78d3SWeongyo Jeong 
1573c7e78d3SWeongyo Jeong struct malo_hal_channel_flags {
1583c7e78d3SWeongyo Jeong 	uint32_t		freqband : 6,
1593c7e78d3SWeongyo Jeong #define MALO_FREQ_BAND_2DOT4GHZ	0x1
1603c7e78d3SWeongyo Jeong 				: 26;		/* reserved */
1613c7e78d3SWeongyo Jeong };
1623c7e78d3SWeongyo Jeong 
1633c7e78d3SWeongyo Jeong struct malo_hal_channel {
1643c7e78d3SWeongyo Jeong 	uint32_t		channel;
1653c7e78d3SWeongyo Jeong 	struct malo_hal_channel_flags flags;
1663c7e78d3SWeongyo Jeong };
1673c7e78d3SWeongyo Jeong 
1683c7e78d3SWeongyo Jeong struct malo_hal_txrate {
1693c7e78d3SWeongyo Jeong 	uint8_t			mcastrate;	/* rate for multicast frames */
1703c7e78d3SWeongyo Jeong 	uint8_t			mgtrate;	/* rate for management frames */
1713c7e78d3SWeongyo Jeong 	struct {
1723c7e78d3SWeongyo Jeong 		uint8_t		trycount;	/* try this many times */
1733c7e78d3SWeongyo Jeong 		uint8_t		rate;		/* use this tx rate */
1743c7e78d3SWeongyo Jeong 	} rateseries[4];			/* rate series */
1753c7e78d3SWeongyo Jeong };
1763c7e78d3SWeongyo Jeong 
1773c7e78d3SWeongyo Jeong struct malo_hal {
1783c7e78d3SWeongyo Jeong 	device_t		mh_dev;
1793c7e78d3SWeongyo Jeong 
1803c7e78d3SWeongyo Jeong 	bus_space_handle_t	mh_ioh;		/* BAR 1 copied from softc */
1813c7e78d3SWeongyo Jeong 	bus_space_tag_t		mh_iot;
1823c7e78d3SWeongyo Jeong 	uint32_t		mh_imask;	/* interrupt mask */
1833c7e78d3SWeongyo Jeong 	int			mh_flags;
1843c7e78d3SWeongyo Jeong #define	MHF_CALDATA		0x0001		/* cal data retrieved */
1853c7e78d3SWeongyo Jeong #define	MHF_FWHANG		0x0002		/* fw appears hung */
1863c7e78d3SWeongyo Jeong 
1873c7e78d3SWeongyo Jeong 	char			mh_mtxname[12];
1883c7e78d3SWeongyo Jeong 	struct mtx		mh_mtx;
1893c7e78d3SWeongyo Jeong 	bus_dma_tag_t		mh_dmat;	/* bus DMA tag for cmd buffer */
1903c7e78d3SWeongyo Jeong 	bus_dmamap_t		mh_dmamap;	/* DMA map for cmd buffer */
1913c7e78d3SWeongyo Jeong 	uint16_t		*mh_cmdbuf;	/* f/w cmd buffer */
1923c7e78d3SWeongyo Jeong 	bus_addr_t		mh_cmdaddr;	/* physaddr of cmd buffer */
1933c7e78d3SWeongyo Jeong 
1943c7e78d3SWeongyo Jeong 	struct malo_hal_caldata	mh_caldata;
1953c7e78d3SWeongyo Jeong 
1963c7e78d3SWeongyo Jeong 	int			mh_debug;
1973c7e78d3SWeongyo Jeong #define MALO_HAL_DEBUG_SENDCMD	0x00000001
1983c7e78d3SWeongyo Jeong #define MALO_HAL_DEBUG_CMDDONE	0x00000002
1993c7e78d3SWeongyo Jeong #define MALO_HAL_DEBUG_IGNHANG	0X00000004
2003c7e78d3SWeongyo Jeong };
2013c7e78d3SWeongyo Jeong 
2023c7e78d3SWeongyo Jeong #define MALO_HAL_LOCK(mh)		mtx_lock(&mh->mh_mtx)
2033c7e78d3SWeongyo Jeong #define MALO_HAL_LOCK_ASSERT(mh)	mtx_assert(&mh->mh_mtx, MA_OWNED)
2043c7e78d3SWeongyo Jeong #define MALO_HAL_UNLOCK(mh)		mtx_unlock(&mh->mh_mtx)
2053c7e78d3SWeongyo Jeong 
2063c7e78d3SWeongyo Jeong struct malo_hal *malo_hal_attach(device_t, uint16_t,
2073c7e78d3SWeongyo Jeong 	    bus_space_handle_t, bus_space_tag_t,
2083c7e78d3SWeongyo Jeong 	    bus_dma_tag_t);
2093c7e78d3SWeongyo Jeong int	malo_hal_fwload(struct malo_hal *, char *, char *);
2103c7e78d3SWeongyo Jeong int	malo_hal_gethwspecs(struct malo_hal *,
2113c7e78d3SWeongyo Jeong 	    struct malo_hal_hwspec *);
2123c7e78d3SWeongyo Jeong void	malo_hal_detach(struct malo_hal *);
2133c7e78d3SWeongyo Jeong void	malo_hal_intrset(struct malo_hal *, uint32_t);
2143c7e78d3SWeongyo Jeong int	malo_hal_setantenna(struct malo_hal *,
2153c7e78d3SWeongyo Jeong 	    enum malo_hal_antenna, int);
2163c7e78d3SWeongyo Jeong int	malo_hal_setradio(struct malo_hal *, int,
2173c7e78d3SWeongyo Jeong 	    enum malo_hal_preamble);
2183c7e78d3SWeongyo Jeong int	malo_hal_setchannel(struct malo_hal *,
2193c7e78d3SWeongyo Jeong 	    const struct malo_hal_channel *);
2203c7e78d3SWeongyo Jeong int	malo_hal_setmaxtxpwr(struct malo_hal *, uint16_t);
2213c7e78d3SWeongyo Jeong int	malo_hal_settxpower(struct malo_hal *, const struct malo_hal_channel *);
2223c7e78d3SWeongyo Jeong int	malo_hal_setpromisc(struct malo_hal *, int);
2233c7e78d3SWeongyo Jeong int	malo_hal_setassocid(struct malo_hal *,
2248b45e0c1SJohn Baldwin 	    const uint8_t[IEEE80211_ADDR_LEN], uint16_t);
2253c7e78d3SWeongyo Jeong void	malo_hal_txstart(struct malo_hal *, int);
2263c7e78d3SWeongyo Jeong void	malo_hal_getisr(struct malo_hal *, uint32_t *);
2273c7e78d3SWeongyo Jeong void	malo_hal_cmddone(struct malo_hal *);
2283c7e78d3SWeongyo Jeong int	malo_hal_prescan(struct malo_hal *);
2293c7e78d3SWeongyo Jeong int	malo_hal_postscan(struct malo_hal *, uint8_t *, uint8_t);
2303c7e78d3SWeongyo Jeong int	malo_hal_set_slot(struct malo_hal *, int);
2313c7e78d3SWeongyo Jeong int	malo_hal_set_rate(struct malo_hal *, uint16_t, uint8_t);
2323c7e78d3SWeongyo Jeong int	malo_hal_setmcast(struct malo_hal *, int, const uint8_t[]);
2333c7e78d3SWeongyo Jeong 
2343c7e78d3SWeongyo Jeong #endif
235