| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a8xx_gpu.c | 79 val = gpu_read(gpu, offset); in a8xx_read_pipe_slice()
140 if (gpu_read(gpu, REG_A8XX_RBBM_STATUS) & in _a8xx_check_idle()
144 return !(gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS) & in _a8xx_check_idle()
158 gpu_read(gpu, REG_A8XX_RBBM_STATUS), in a8xx_idle()
159 gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS), in a8xx_idle()
160 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a8xx_idle()
161 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a8xx_idle()
423 *dest++ = gpu_read(gpu, reglist->regs[i]); in a8xx_patch_pwrup_reglist()
433 *dest++ = gpu_read(gpu, reglist->regs[i]); in a8xx_patch_pwrup_reglist()
652 gpu_read(gpu, REG_A6XX_GBIF_HALT); in hw_init()
[all …]
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| H A D | a2xx_gpu.c | 277 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a2xx_recover()
285 gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET); in a2xx_recover()
309 if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) & in a2xx_idle()
324 mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL); in a2xx_irq()
327 status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS); in a2xx_irq()
331 gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT)); in a2xx_irq()
337 status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS); in a2xx_irq()
347 status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS); in a2xx_irq()
454 gpu_read(gpu, REG_A2XX_RBBM_STATUS)); in a2xx_dump()
467 state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS); in a2xx_gpu_state_get()
[all …]
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| H A D | a3xx_gpu.c | 374 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover()
382 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
408 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
423 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
477 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
490 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get()
507 ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); in a3xx_get_rptr()
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| H A D | a5xx_gpu.h | 146 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
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| H A D | a5xx_preempt.c | 194 status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL); in a5xx_preempt_irq()
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| /linux/drivers/gpu/drm/etnaviv/ |
| H A D | etnaviv_gpu.c | 218 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
219 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
220 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
221 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
365 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
373 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
375 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
376 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
377 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); in etnaviv_hw_identify()
384 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); in etnaviv_hw_identify()
[all …]
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| H A D | etnaviv_sched.c | 54 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
62 primid = gpu_read(gpu, VIVS_MC_PROFILE_FE_READ); in etnaviv_sched_timedout_job()
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| H A D | etnaviv_iommu_v2.c | 172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
196 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
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| H A D | etnaviv_gpu.h | 175 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() function
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| H A D | etnaviv_dump.c | 94 reg->value = cpu_to_le32(gpu_read(gpu, read_addr)); in etnaviv_core_dump_registers()
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| /linux/drivers/gpu/drm/msm/ |
| H A D | msm_gpu.h | 601 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) in gpu_read() function
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| /linux/drivers/gpu/drm/panthor/ |
| H A D | panthor_mmu.c | 1734 fault_status = gpu_read(ptdev, AS_FAULTSTATUS(as)); in panthor_mmu_irq_handler()
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