79 	val = gpu_read(gpu, offset);  in a8xx_read_pipe_slice()
140 	if (gpu_read(gpu, REG_A8XX_RBBM_STATUS) &  in _a8xx_check_idle()
144 	return !(gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS) &  in _a8xx_check_idle()
158 			gpu_read(gpu, REG_A8XX_RBBM_STATUS),  in a8xx_idle()
159 			gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS),  in a8xx_idle()
160 			gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a8xx_idle()
161 			gpu_read(gpu, REG_A6XX_CP_RB_WPTR));  in a8xx_idle()
423 			*dest++ = gpu_read(gpu, reglist->regs[i]);  in a8xx_patch_pwrup_reglist()
433 			*dest++ = gpu_read(gpu, reglist->regs[i]);  in a8xx_patch_pwrup_reglist()
652 	gpu_read(gpu, REG_A6XX_GBIF_HALT);  in hw_init()
655 	gpu_read(gpu, REG_A8XX_RBBM_GBIF_HALT);  in hw_init()
876 	DRM_DEV_INFO(&gpu->pdev->dev, "status:   %08x\n", gpu_read(gpu, REG_A8XX_RBBM_STATUS));  in a8xx_dump()
959 	val = gpu_read(gpu, REG_A8XX_UCHE_CLIENT_PF);  in a8xx_uche_fault_block()
1016 			gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(0)),  in a8xx_fault_handler()
1017 			gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(1)),  in a8xx_fault_handler()
1018 			gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(2)),  in a8xx_fault_handler()
1019 			gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(3)),  in a8xx_fault_handler()
1030 	u32 status = gpu_read(gpu, REG_A8XX_CP_INTERRUPT_STATUS_GLOBAL);  in a8xx_cp_hw_err_irq()
1100 	return gpu_read(gpu, REG_A8XX_CP_SQE_UCODE_DBG_DATA_PIPE);  in gpu_periph_read()
1139 	if (gpu_read(gpu, REG_A8XX_RBBM_MISC_STATUS) & A8XX_RBBM_MISC_STATUS_SMMU_STALLED_ON_FAULT)  in a8xx_fault_detect_irq()
1152 		gpu_read(gpu, REG_A8XX_RBBM_STATUS), gpu_read(gpu, REG_A8XX_RBBM_GFX_STATUS));  in a8xx_fault_detect_irq()
1158 		gpu_read(gpu, REG_A8XX_RBBM_GFX_BR_STATUS),  in a8xx_fault_detect_irq()
1159 		gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a8xx_fault_detect_irq()
1160 		gpu_read(gpu, REG_A6XX_CP_RB_WPTR),  in a8xx_fault_detect_irq()
1173 		gpu_read(gpu, REG_A8XX_RBBM_GFX_BV_STATUS),  in a8xx_fault_detect_irq()
1174 		gpu_read(gpu, REG_A8XX_CP_RB_RPTR_BV),  in a8xx_fault_detect_irq()
1175 		gpu_read(gpu, REG_A6XX_CP_RB_WPTR),  in a8xx_fault_detect_irq()
1196 	status = gpu_read(gpu, REG_A8XX_RBBM_SW_FUSE_INT_STATUS);  in a8xx_sw_fuse_violation_irq()
1216 	u32 status = gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS);  in a8xx_irq()
1229 		rl0 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_0);  in a8xx_irq()
1230 		rl1 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_1);  in a8xx_irq()
1304 		spin_until(gpu_read(gpu, REG_A8XX_RBBM_GBIF_HALT_ACK) & 1);  in a8xx_bus_clear_pending_transactions()
1309 	spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &  in a8xx_bus_clear_pending_transactions()
1314 	spin_until((gpu_read(gpu,  REG_A6XX_GBIF_HALT_ACK) &  in a8xx_bus_clear_pending_transactions()