218 		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);  in etnaviv_hw_specs()
219 		specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);  in etnaviv_hw_specs()
220 		specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);  in etnaviv_hw_specs()
221 		specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);  in etnaviv_hw_specs()
365 	chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);  in etnaviv_hw_identify()
373 		u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);  in etnaviv_hw_identify()
375 		gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);  in etnaviv_hw_identify()
376 		gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);  in etnaviv_hw_identify()
377 		gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);  in etnaviv_hw_identify()
384 			gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);  in etnaviv_hw_identify()
385 			gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);  in etnaviv_hw_identify()
401 			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);  in etnaviv_hw_identify()
442 	gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);  in etnaviv_hw_identify()
471 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);  in etnaviv_hw_identify()
476 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);  in etnaviv_hw_identify()
478 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);  in etnaviv_hw_identify()
480 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);  in etnaviv_hw_identify()
482 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);  in etnaviv_hw_identify()
484 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);  in etnaviv_hw_identify()
519 		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_gpu_update_clock()
586 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_hw_reset()
595 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_hw_reset()
613 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_hw_reset()
614 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_hw_reset()
769 	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {  in etnaviv_gpu_hw_init()
772 		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;  in etnaviv_gpu_hw_init()
795 		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);  in etnaviv_gpu_hw_init()
804 		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);  in etnaviv_gpu_hw_init()
955 	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in verify_dma()
956 	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);  in verify_dma()
959 		debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in verify_dma()
960 		debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);  in verify_dma()
982 	dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);  in etnaviv_gpu_debugfs()
983 	dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);  in etnaviv_gpu_debugfs()
984 	axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);  in etnaviv_gpu_debugfs()
985 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_gpu_debugfs()
1095 		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);  in etnaviv_gpu_debugfs()
1096 		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);  in etnaviv_gpu_debugfs()
1097 		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);  in etnaviv_gpu_debugfs()
1477 	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in sync_point_worker()
1549 	status = gpu_read(gpu, status_reg);  in dump_mmu_fault()
1571 				    i, reason, gpu_read(gpu, address_reg));  in dump_mmu_fault()
1580 	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);  in irq_handler()
1691 		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_gpu_wait_idle()
1996 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;  in etnaviv_gpu_rpm_suspend()