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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
H A Dhikey960-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/hisi.h>
12 range: gpio-range { label
13 #pinctrl-single,gpio-range-cells = <3>;
17 compatible = "pinctrl-single";
19 #pinctrl-cells = <1>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
23 /* pin base, nr pins & gpio function */
[all …]
H A Dhikey970-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range { label
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
[all …]
/linux/drivers/pinctrl/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
7 * Based on bits of regulator core, gpio core and clk core
27 #include <linux/gpio.h>
28 #include <linux/gpio/driver.h>
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
77 return pctldev->desc->name; in pinctrl_dev_get_name()
83 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
89 return pctldev->driver_data; in pinctrl_dev_get_drvdata()
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H A Dpinctrl-at91.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/gpio/driver.h>
29 #include "pinctrl-at91.h"
38 * struct at91_gpio_chip: at91 gpio chip
39 * @chip: gpio chip
40 * @range: gpio range
49 * @id: gpio chip identifier
53 struct pinctrl_gpio_range range; member
114 * struct at91_pmx_func - describes AT91 pinmux functions
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 range of pin control registers can vary from one to many for each controller
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
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H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad7606.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7605-4.pdf
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-16.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-18.pdf
19 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7607.pdf
[all …]
/linux/include/linux/pinctrl/
H A Dpinmux.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
7 * Based on bits of regulator core, gpio core and clk core
20 * struct pinmux_ops - pinmux operations, to be implemented by pin controller
44 * @gpio_request_enable: requests and enables GPIO on a certain pin.
45 * Implement this only if you can mux every pin individually as GPIO
[all...]
/linux/Documentation/driver-api/
H A Dpin-control.rst9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
30 be sparse - i.e. there may be gaps in the space with numbers where no
60 .. code-block:: c
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/linux/Documentation/devicetree/bindings/iio/addac/
H A Dadi,ad74115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
30 spi-max-frequency:
33 spi-cpol: true
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/linux/drivers/gpio/
H A Dgpio-tangier.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Tangier GPIO functions
15 #include <linux/gpio/driver.h>
35 * struct tng_wake_regs - Platform specific wake registers
47 * struct tng_gpio_pinrange - Map pin numbers to gpio numbers
48 * @gpio_base: Starting GPIO number of this range
49 * @pin_base: Starting pin number of this range
50 * @npins: Number of pins in this range
62 .npins = (gend) - (gstart) + 1, \
66 * struct tng_gpio_pin_info - Platform specific pinout information
[all …]
H A Dgpio-tangier.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Tangier GPIO driver
22 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/gpio/driver.h>
30 #include "gpio-tangier.h"
46 * struct tng_gpio_context - Context to be saved during suspend-resume
69 return priv->reg_base + reg + reg_offset * 4; in gpio_reg()
80 return priv->reg_base + reg + reg_offset * 4; in gpio_reg_and_bit()
101 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_set()
117 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_direction_input()
[all …]
H A Dgpio-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/gpio/driver.h>
16 #include <dt-bindings/gpio/uniphier-gpio.h>
43 * Unfortunately, the GPIO port registers are not contiguous because in uniphier_gpio_bank_to_reg()
44 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. in uniphier_gpio_bank_to_reg()
65 spin_lock_irqsave(&priv->lock, flags); in uniphier_gpio_reg_update()
66 tmp = readl(priv->regs + reg); in uniphier_gpio_reg_update()
69 writel(tmp, priv->regs + reg); in uniphier_gpio_reg_update()
70 spin_unlock_irqrestore(&priv->lock, flags); in uniphier_gpio_reg_update()
107 return !!(readl(priv->regs + reg_offset) & mask); in uniphier_gpio_offset_read()
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
/linux/drivers/iio/adc/
H A Dad7606.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 * Range of channels from a group are stored in 2 registers.
22 * For channels from second group(8-15) the order is the same, only with
26 /* The range of the channel is stored in 2 bits */
34 * Range for AD7606B channels are stored in registers starting with address 0x3.
35 * Each register stores range for 2 channels(4 bits per channel).
55 * struct ad7606_chip_info - chip specific information
70 * @calib_offset_avail: pointer to offset calibration range/limits array
71 * @calib_phase_avail: pointer to phase calibration range/limits array
91 * struct ad7606_chan_info - channel configuration
[all …]
/linux/arch/arm/mach-s3c/
H A Dgpio-cfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * S3C Platform - GPIO pin configuration
11 /* This file contains the necessary definitions to get the basic gpio
13 * changing the pull-{up,down} configurations.
27 /* forward declaration if gpio-core.h hasn't been included */
31 * struct samsung_gpio_cfg GPIO configuration
33 * @get_pull: Read the current pull configuration for the GPIO
34 * @set_pull: Set the current pull configuration for the GPIO
35 * @set_config: Set the current configuration for the GPIO
36 * @get_config: Read the current configuration for the GPIO
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h700-anbernic-rg35xx-h.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
7 #include "sun50i-h700-anbernic-rg35xx-plus.dts"
11 compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700";
13 adc-joystick {
14 compatible = "adc-joystick";
15 io-channels = <&adc_mux 0>,
19 pinctrl-0 = <&joy_mux_pin>;
20 pinctrl-names = "default";
21 poll-interval = <60>;
22 #address-cells = <1>;
[all …]
/linux/drivers/pinctrl/renesas/
H A Dgpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Pin Function Controller GPIO driver.
6 * Copyright (C) 2009 - 2012 Paul Mundt
10 #include <linux/gpio/driver.h>
40 return chip->pfc; in gpio_to_pfc()
47 int idx = sh_pfc_get_pin_index(chip->pfc, offset); in gpio_get_data_reg()
48 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; in gpio_get_data_reg()
50 *reg = &chip->regs[gpio_pin->dreg]; in gpio_get_data_reg()
51 *bit = gpio_pin->dbit; in gpio_get_data_reg()
57 phys_addr_t address = dreg->reg; in gpio_read_data_reg()
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dti,tps62360.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laxman Dewangan <ldewangan@nvidia.com>
13 The TPS6236x are a family of step down dc-dc converter with
14 an input voltage range of 2.5V to 5.5V. The devices provide
15 up to 3A peak load current, and an output voltage range of
22 - $ref: regulator.yaml#
27 - ti,tps62360
28 - ti,tps62361
[all …]
H A Dpwm-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
23 is given to the user if the assumptions made in continuous-voltage mode do
[all …]
/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908-samsung-coreprimevelte.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/linux-event-codes.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 stdout-path = "serial0:115200n8";
24 compatible = "simple-framebuffer";
39 reserved-memory {
40 #address-cells = <2>;
41 #size-cells = <2>;
[all …]

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