Lines Matching +full:gpio +full:- +full:range
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
43 clock-latency = <1000000>;
54 compatible = "marvell,armada-xp-pcie";
58 #address-cells = <3>;
59 #size-cells = <2>;
61 msi-parent = <&mpic>;
62 bus-range = <0x00 0xff>;
97 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
99 #address-cells = <3>;
100 #size-cells = <2>;
101 interrupt-names = "intx";
102 interrupts-extended = <&mpic 58>;
103 #interrupt-cells = <1>;
106 bus-range = <0x00 0xff>;
107 interrupt-map-mask = <0 0 0 7>;
108 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
112 marvell,pcie-port = <0>;
113 marvell,pcie-lane = <0>;
117 pcie1_intc: interrupt-controller {
118 interrupt-controller;
119 #interrupt-cells = <1>;
125 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
127 #address-cells = <3>;
128 #size-cells = <2>;
129 interrupt-names = "intx";
130 interrupts-extended = <&mpic 59>;
131 #interrupt-cells = <1>;
134 bus-range = <0x00 0xff>;
135 interrupt-map-mask = <0 0 0 7>;
136 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
140 marvell,pcie-port = <0>;
141 marvell,pcie-lane = <1>;
145 pcie2_intc: interrupt-controller {
146 interrupt-controller;
147 #interrupt-cells = <1>;
153 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
155 #address-cells = <3>;
156 #size-cells = <2>;
157 interrupt-names = "intx";
158 interrupts-extended = <&mpic 60>;
159 #interrupt-cells = <1>;
162 bus-range = <0x00 0xff>;
163 interrupt-map-mask = <0 0 0 7>;
164 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
168 marvell,pcie-port = <0>;
169 marvell,pcie-lane = <2>;
173 pcie3_intc: interrupt-controller {
174 interrupt-controller;
175 #interrupt-cells = <1>;
181 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
183 #address-cells = <3>;
184 #size-cells = <2>;
185 interrupt-names = "intx";
186 interrupts-extended = <&mpic 61>;
187 #interrupt-cells = <1>;
190 bus-range = <0x00 0xff>;
191 interrupt-map-mask = <0 0 0 7>;
192 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
196 marvell,pcie-port = <0>;
197 marvell,pcie-lane = <3>;
201 pcie4_intc: interrupt-controller {
202 interrupt-controller;
203 #interrupt-cells = <1>;
209 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
211 #address-cells = <3>;
212 #size-cells = <2>;
213 interrupt-names = "intx";
214 interrupts-extended = <&mpic 62>;
215 #interrupt-cells = <1>;
218 bus-range = <0x00 0xff>;
219 interrupt-map-mask = <0 0 0 7>;
220 interrupt-map = <0 0 0 1 &pcie5_intc 0>,
224 marvell,pcie-port = <1>;
225 marvell,pcie-lane = <0>;
229 pcie5_intc: interrupt-controller {
230 interrupt-controller;
231 #interrupt-cells = <1>;
237 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
239 #address-cells = <3>;
240 #size-cells = <2>;
241 interrupt-names = "intx";
242 interrupts-extended = <&mpic 63>;
243 #interrupt-cells = <1>;
246 bus-range = <0x00 0xff>;
247 interrupt-map-mask = <0 0 0 7>;
248 interrupt-map = <0 0 0 1 &pcie6_intc 0>,
252 marvell,pcie-port = <1>;
253 marvell,pcie-lane = <1>;
257 pcie6_intc: interrupt-controller {
258 interrupt-controller;
259 #interrupt-cells = <1>;
265 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
267 #address-cells = <3>;
268 #size-cells = <2>;
269 interrupt-names = "intx";
270 interrupts-extended = <&mpic 64>;
271 #interrupt-cells = <1>;
274 bus-range = <0x00 0xff>;
275 interrupt-map-mask = <0 0 0 7>;
276 interrupt-map = <0 0 0 1 &pcie7_intc 0>,
280 marvell,pcie-port = <1>;
281 marvell,pcie-lane = <2>;
285 pcie7_intc: interrupt-controller {
286 interrupt-controller;
287 #interrupt-cells = <1>;
293 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
295 #address-cells = <3>;
296 #size-cells = <2>;
297 interrupt-names = "intx";
298 interrupts-extended = <&mpic 65>;
299 #interrupt-cells = <1>;
302 bus-range = <0x00 0xff>;
303 interrupt-map-mask = <0 0 0 7>;
304 interrupt-map = <0 0 0 1 &pcie8_intc 0>,
308 marvell,pcie-port = <1>;
309 marvell,pcie-lane = <3>;
313 pcie8_intc: interrupt-controller {
314 interrupt-controller;
315 #interrupt-cells = <1>;
321 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
323 #address-cells = <3>;
324 #size-cells = <2>;
325 interrupt-names = "intx";
326 interrupts-extended = <&mpic 99>;
327 #interrupt-cells = <1>;
330 bus-range = <0x00 0xff>;
331 interrupt-map-mask = <0 0 0 7>;
332 interrupt-map = <0 0 0 1 &pcie9_intc 0>,
336 marvell,pcie-port = <2>;
337 marvell,pcie-lane = <0>;
341 pcie9_intc: interrupt-controller {
342 interrupt-controller;
343 #interrupt-cells = <1>;
348 internal-regs {
349 gpio0: gpio@18100 {
350 compatible = "marvell,armada-370-gpio",
351 "marvell,orion-gpio";
353 reg-names = "gpio", "pwm";
355 gpio-controller;
356 #gpio-cells = <2>;
357 #pwm-cells = <2>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
364 gpio1: gpio@18140 {
365 compatible = "marvell,armada-370-gpio",
366 "marvell,orion-gpio";
368 reg-names = "gpio", "pwm";
370 gpio-controller;
371 #gpio-cells = <2>;
372 #pwm-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
379 gpio2: gpio@18180 {
380 compatible = "marvell,armada-370-gpio",
381 "marvell,orion-gpio";
384 gpio-controller;
385 #gpio-cells = <2>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
392 compatible = "marvell,armada-xp-neta";
403 compatible = "marvell,mv78260-pinctrl";