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/linux/sound/arm/
H A Dpxa2xx-ac97-lib.c123 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa25x()
128 …writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything bu… in pxa_ac97_cold_pxa25x()
129 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */ in pxa_ac97_cold_pxa25x()
133 writel(GCR_COLD_RST, ac97_reg_base + GCR); in pxa_ac97_cold_pxa25x()
145 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa27x()
152 …writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything bu… in pxa_ac97_cold_pxa27x()
153 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */ in pxa_ac97_cold_pxa27x()
161 writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR); in pxa_ac97_cold_pxa27x()
171 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa3xx()
177 writel(0, ac97_reg_base + GCR); in pxa_ac97_cold_pxa3xx()
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/linux/arch/s390/kvm/
H A Dguestdbg.c62 u64 *cr9 = &vcpu->arch.sie_block->gcr[9]; in enable_all_hw_bp()
63 u64 *cr10 = &vcpu->arch.sie_block->gcr[10]; in enable_all_hw_bp()
64 u64 *cr11 = &vcpu->arch.sie_block->gcr[11]; in enable_all_hw_bp()
102 u64 *cr9 = &vcpu->arch.sie_block->gcr[9]; in enable_all_hw_wp()
103 u64 *cr10 = &vcpu->arch.sie_block->gcr[10]; in enable_all_hw_wp()
104 u64 *cr11 = &vcpu->arch.sie_block->gcr[11]; in enable_all_hw_wp()
132 vcpu->arch.guestdbg.cr0 = vcpu->arch.sie_block->gcr[0]; in kvm_s390_backup_guest_per_regs()
133 vcpu->arch.guestdbg.cr9 = vcpu->arch.sie_block->gcr[9]; in kvm_s390_backup_guest_per_regs()
134 vcpu->arch.guestdbg.cr10 = vcpu->arch.sie_block->gcr[10]; in kvm_s390_backup_guest_per_regs()
135 vcpu->arch.guestdbg.cr11 = vcpu->arch.sie_block->gcr[11]; in kvm_s390_backup_guest_per_regs()
[all …]
H A Dgaccess.c253 asce->val = vcpu->arch.sie_block->gcr[1]; in ar_translation()
256 asce->val = vcpu->arch.sie_block->gcr[7]; in ar_translation()
264 ald_addr = vcpu->arch.sie_block->gcr[5]; in ar_translation()
266 ald_addr = vcpu->arch.sie_block->gcr[2]; in ar_translation()
299 eax = (vcpu->arch.sie_block->gcr[8] >> 16) & 0xffff; in ar_translation()
427 asce->val = vcpu->arch.sie_block->gcr[1]; in get_vcpu_asce()
430 asce->val = vcpu->arch.sie_block->gcr[7]; in get_vcpu_asce()
433 asce->val = vcpu->arch.sie_block->gcr[13]; in get_vcpu_asce()
483 ctlreg0.val = vcpu->arch.sie_block->gcr[0]; in guest_translate_gva()
643 union ctlreg0 ctlreg0 = {.val = vcpu->arch.sie_block->gcr[0]}; in low_address_protection_enabled()
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H A Dinterrupt.c121 !(vcpu->arch.sie_block->gcr[0] & CR0_CLOCK_COMPARATOR_SUBMASK)) in ckc_interrupts_enabled()
134 if (vcpu->arch.sie_block->gcr[0] & CR0_CLOCK_COMPARATOR_SIGN) { in ckc_irq_pending()
146 (vcpu->arch.sie_block->gcr[0] & CR0_CPU_TIMER_SUBMASK); in cpu_timer_interrupts_enabled()
303 if (!(vcpu->arch.sie_block->gcr[6] & isc_to_isc_bits(i))) in disable_iscs()
323 if (!(vcpu->arch.sie_block->gcr[0] & CR0_EXTERNAL_CALL_SUBMASK)) in deliverable_irqs()
325 if (!(vcpu->arch.sie_block->gcr[0] & CR0_EMERGENCY_SIGNAL_SUBMASK)) in deliverable_irqs()
327 if (!(vcpu->arch.sie_block->gcr[0] & CR0_CLOCK_COMPARATOR_SUBMASK)) in deliverable_irqs()
329 if (!(vcpu->arch.sie_block->gcr[0] & CR0_CPU_TIMER_SUBMASK)) in deliverable_irqs()
331 if (!(vcpu->arch.sie_block->gcr[0] & CR0_SERVICE_SIGNAL_SUBMASK)) { in deliverable_irqs()
347 if (!(vcpu->arch.sie_block->gcr[14] & in deliverable_irqs()
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H A Dvsie.c446 memcpy(scb_o->gcr, scb_s->gcr, 128); in unshadow_scb()
512 memcpy(scb_s->gcr, scb_o->gcr, 128); in shadow_scb()
1069 cr0.val = vcpu->arch.sie_block->gcr[0]; in vsie_handle_mvpg()
1260 asce.val = vcpu->arch.sie_block->gcr[1]; in acquire_gmap_shadow()
1261 cr0.val = vcpu->arch.sie_block->gcr[0]; in acquire_gmap_shadow()
H A Dsigp.c77 p_asn = dst_vcpu->arch.sie_block->gcr[4] & 0xffff; /* Primary ASN */ in __sigp_conditional_emergency()
78 s_asn = dst_vcpu->arch.sie_block->gcr[3] & 0xffff; /* Secondary ASN */ in __sigp_conditional_emergency()
/linux/Documentation/devicetree/bindings/soc/nuvoton/
H A Dnuvoton,npcm-gcr.yaml4 $id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml#
14 The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
22 - nuvoton,wpcm450-gcr
23 - nuvoton,npcm750-gcr
24 - nuvoton,npcm845-gcr
40 gcr: syscon@800000 {
41 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
/linux/drivers/soc/nuvoton/
H A Dwpcm450-soc.c52 struct regmap *gcr; in wpcm450_soc_init() local
59 gcr = syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr"); in wpcm450_soc_init()
60 if (IS_ERR(gcr)) in wpcm450_soc_init()
61 return PTR_ERR(gcr); in wpcm450_soc_init()
62 ret = regmap_read(gcr, GCR_PDID, &pdid); in wpcm450_soc_init()
67 pr_warn("Unknown chip ID in GCR.PDID: 0x%06x\n", PDID_CHIP(pdid)); in wpcm450_soc_init()
73 pr_warn("Unknown chip revision in GCR.PDID: 0x%02x\n", PDID_REV(pdid)); in wpcm450_soc_init()
/linux/include/linux/mfd/
H A Dintel_pmc_bxt.h5 /* GCR reg offsets from GCR base */
17 * @gcr_mem_base: Virtual base address of GCR (Global Configuration Registers)
18 * @gcr_lock: Lock used to serialize access to GCR registers
/linux/drivers/mfd/
H A Dintel_pmc_bxt.c73 * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register
75 * @offset: offset of GCR register from GCR address base
78 * Reads the 64-bit PMC GCR register at given offset.
96 * intel_pmc_gcr_update() - Update PMC GCR register bits
98 * @offset: offset of GCR register from GCR address base
102 * Updates the bits of given GCR register as specified by
325 /* GCR registers */ in intel_pmc_get_resources()
/linux/arch/arm/mach-npcm/
H A Dplatsmp.c28 gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr"); in npcm7xx_smp_boot_secondary()
30 pr_err("no gcr device node\n"); in npcm7xx_smp_boot_secondary()
36 pr_err("could not iomap gcr"); in npcm7xx_smp_boot_secondary()
/linux/Documentation/devicetree/bindings/reset/
H A Dnuvoton,npcm750-reset.yaml33 description: a phandle to access GCR registers.
69 nuvoton,sysgcr = <&gcr>;
/linux/Documentation/devicetree/bindings/media/
H A Dnuvoton,npcm-vcd.yaml33 description: phandle to access GCR (Global Control Register) registers.
69 nuvoton,sysgcr = <&gcr>;
/linux/sound/soc/stm/
H A Dstm32_sai.c88 /* Enable peripheral clock to allow GCR register access */ in stm32_sai_sync_conf_client()
105 /* Enable peripheral clock to allow GCR register access */ in stm32_sai_sync_conf_provider()
275 sai->gcr = readl_relaxed(sai->base); in stm32_sai_suspend()
290 writel_relaxed(sai->gcr, sai->base); in stm32_sai_resume()
/linux/drivers/gpu/drm/stm/
H A Dlvds.c176 u32 GCR; /* Global Control Register */ member
206 .GCR = 0x0,
232 .GCR = 0x0,
363 lvds_set(lvds, phy->base + phy->ofs.GCR, lvds_gcr); in lvds_pll_enable()
573 lvds_set(lvds, phy->base + phy->ofs.GCR, PHY_GCR_DIV_RSTN | PHY_GCR_RSTZ); in lvds_pixel_clk_enable()
587 lvds_set(lvds, phy->base + phy->ofs.GCR, PHY_GCR_DIV_RSTN | PHY_GCR_RSTZ); in lvds_pixel_clk_enable()
612 lvds_clear(lvds, lvds->primary->base + lvds->primary->ofs.GCR, in lvds_pixel_clk_disable()
616 lvds_clear(lvds, lvds->primary->base + lvds->primary->ofs.GCR, in lvds_pixel_clk_disable()
621 lvds_clear(lvds, lvds->secondary->base + lvds->secondary->ofs.GCR, in lvds_pixel_clk_disable()
625 lvds_clear(lvds, lvds->secondary->base + lvds->secondary->ofs.GCR, in lvds_pixel_clk_disable()
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_82598.c37 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); in ixgbe_set_pcie_completion_timeout() local
44 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) in ixgbe_set_pcie_completion_timeout()
49 * timeout of 10ms to 250ms through the GCR register in ixgbe_set_pcie_completion_timeout()
51 if (!(gcr & IXGBE_GCR_CAP_VER2)) { in ixgbe_set_pcie_completion_timeout()
52 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; in ixgbe_set_pcie_completion_timeout()
66 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; in ixgbe_set_pcie_completion_timeout()
67 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); in ixgbe_set_pcie_completion_timeout()
/linux/arch/powerpc/kvm/
H A Dmpic.c216 uint32_t gcr; /* Global configuration register */ member
516 opp->gcr = GCR_RESET; in openpic_reset()
558 opp->gcr = 0; in openpic_reset()
684 opp->gcr &= ~opp->mpic_mode_mask; in openpic_gcr_write()
685 opp->gcr |= val & opp->mpic_mode_mask; in openpic_gcr_write()
713 case 0x1020: /* GCR */ in openpic_gbl_write()
760 case 0x1020: /* GCR */ in openpic_gbl_read()
761 retval = opp->gcr; in openpic_gbl_read()
1184 if ((opp->gcr & opp->mpic_mode_mask) == GCR_MODE_PROXY) in kvmppc_mpic_set_epr()
1763 /* This might need to be changed if GCR gets extended */ in kvmppc_mpic_connect_vcpu()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnuvoton,npcm845-pinctrl.yaml33 description: a phandle to access GCR registers.
195 nuvoton,sysgcr = <&gcr>;
/linux/Documentation/devicetree/bindings/arm/cpu-enable-method/
H A Dnuvoton,npcm750-smp15 "nuvoton,npcm750-gcr".
/linux/Documentation/devicetree/bindings/i2c/
H A Dnuvoton,npcm7xx-i2c.yaml74 nuvoton,sys-mgr = <&gcr>;
/linux/Documentation/devicetree/bindings/mmc/
H A Dnuvoton,ma35d1-sdhci.yaml50 description: phandle to access GCR (Global Control Register) registers.
/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-wpcm450.dtsi55 gcr: syscon@b0000000 { label
56 compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd";
/linux/drivers/media/platform/nuvoton/
H A Dnpcm-video.c651 struct regmap *gcr = video->gcr_regmap; in npcm_video_gfx_reset() local
653 regmap_update_bits(gcr, INTCR2, INTCR2_GIRST2, INTCR2_GIRST2); in npcm_video_gfx_reset()
655 regmap_update_bits(gcr, INTCR2, INTCR2_GIRST2, 0); in npcm_video_gfx_reset()
752 struct regmap *gcr = video->gcr_regmap, *vcd = video->vcd_regmap; in npcm_video_init_reg() local
755 regmap_update_bits(gcr, INTCR, INTCR_DEHS, 0); in npcm_video_init_reg()
758 regmap_update_bits(gcr, INTCR, INTCR_GFXIFDIS, 0); in npcm_video_init_reg()
761 regmap_update_bits(gcr, INTCR2, INTCR2_GIHCRST | INTCR2_GIVCRST, in npcm_video_init_reg()
H A Dnpcm-regs.h113 /* GCR Registers */
/linux/drivers/net/ethernet/intel/e1000e/
H A Dmac.c1687 u32 gcr; in e1000e_set_pcie_no_snoop() local
1690 gcr = er32(GCR); in e1000e_set_pcie_no_snoop()
1691 gcr &= ~(PCIE_NO_SNOOP_ALL); in e1000e_set_pcie_no_snoop()
1692 gcr |= no_snoop; in e1000e_set_pcie_no_snoop()
1693 ew32(GCR, gcr); in e1000e_set_pcie_no_snoop()

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