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/titanic_51/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h3 #define ATC_REG_ATC_NUM_SETS 0x110000UL //ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32
9 #define ATC_REG_ATC_STALL_SEQ_0 0x110018UL //ACCESS:RW DataWidth:0x6 Description: Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SP
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