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/linux/Documentation/devicetree/bindings/net/
H A Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
/linux/arch/powerpc/include/asm/
H A Dcell-pmu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cell Broadband Engine Performance Monitor
15 /* The Cell PMU has four hardware performance counters, which can be
16 * configured as four 32-bit counters or eight 16-bit counters.
22 #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
52 #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
/linux/Documentation/devicetree/bindings/gpio/
H A Dcavium-octeon-gpio.txt4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
19 connected to the interrupt source. The second cell is the interrupt
20 triggering protocol and may have one of four values:
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dstericsson,u8500-clks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
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H A Dpistachio-clock.txt4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
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H A Dmicrochip,mpfs-ccc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Dooley <conor.dooley@microchip.com>
14 these blocks contains two PLLs and 2 DLLs & are located in the four corners of
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
25 - description: PLL1's control registers
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Dqcom-pm8xxx-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/qcom-pm8xxx-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Satya Priya <quic_c_skakit@quicinc.com>
15 - enum:
16 - qcom,pm8058-rtc
17 - qcom,pm8921-rtc
18 - qcom,pm8941-rtc
19 - qcom,pmk8350-rtc
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/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,madera.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 include/dt-bindings/sound/madera.h
26 - $ref: dai-common.yaml#
29 '#sound-dai-cells':
31 The first cell indicating the audio interface.
37 of 24 cells, with four cells per input in the order INnAL,
38 INnAR INnBL INnBR. For non-muxed inputs the first two cells
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/linux/Documentation/devicetree/bindings/dma/
H A Drenesas,rzn1-dmamux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: dma-router.yaml#
17 const: renesas,rzn1-dmamux
23 '#dma-cells':
26 The first four cells are dedicated to the master DMA controller. The fifth
27 cell gives the DMA mux bit index that must be set starting from 0. The
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dti,lp87561-q1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87561-q1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI LP87561-Q1 single 4-phase output buck converter
10 - Keerthy <j-keerthy@ti.com>
14 const: ti,lp87561-q1
20 reset-gpios:
24 gpio-controller: true
26 '#gpio-cells':
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H A Dti,lp87524-q1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87524-q1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI LP87524-Q1 four 1-phase output buck converter
10 - Keerthy <j-keerthy@ti.com>
14 const: ti,lp87524-q1
20 reset-gpios:
24 gpio-controller: true
26 '#gpio-cells':
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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 It converts two groups of four 7/10 bits of CMOS data into two
15 groups of four data lanes of LVDS data streams. A phase-locked
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional parameters (currently unused).
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-generic.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
8 Generic line-based metadata formats
14 These generic line-based metadata formats define the memory layout of the data
17 .. _v4l2-meta-fmt-generic-8:
20 -----------------------
22 The V4L2_META_FMT_GENERIC_8 format is a plain 8-bit metadata format. This format
23 is used on CSI-2 for 8 bits per :term:`Data Unit`.
26 packed into one 16-bit Data Unit. Otherwise the 16 bits per pixel dataformat is
27 :ref:`V4L2_META_FMT_GENERIC_CSI2_16 <v4l2-meta-fmt-generic-csi2-16>`.
30 Each cell is one byte. "M" denotes a byte of metadata.
[all …]
H A Dpixfmt-srggb14p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14P:
4 .. _v4l2-pix-fmt-sbggr14p:
5 .. _v4l2-pix-fmt-sgbrg14p:
6 .. _v4l2-pix-fmt-sgrbg14p:
17 14-bit packed Bayer formats
23 These four pixel formats are packed raw sRGB / Bayer formats with 14
24 bits per colour. Every four consecutive samples are packed into seven
25 bytes. Each of the first four bytes contain the eight high order bits
29 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
[all …]
H A Dpixfmt-srggb10p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10P:
4 .. _v4l2-pix-fmt-sbggr10p:
5 .. _v4l2-pix-fmt-sgbrg10p:
6 .. _v4l2-pix-fmt-sgrbg10p:
16 10-bit packed Bayer formats
22 These four pixel formats are packed raw sRGB / Bayer formats with 10
23 bits per sample. Every four consecutive samples are packed into 5
28 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
29 with alternating green-red and green-blue rows. They are conventionally
[all …]
H A Dpixfmt-srggb12p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12P:
4 .. _v4l2-pix-fmt-sbggr12p:
5 .. _v4l2-pix-fmt-sgbrg12p:
6 .. _v4l2-pix-fmt-sgrbg12p:
13 12-bit packed Bayer formats
14 ---------------------------
20 These four pixel formats are packed raw sRGB / Bayer formats with 12
23 the pixels, and the third byte contains the four least significants
26 Each n-pixel row contains n/2 green samples and n/2 blue or red
[all …]
H A Dpixfmt-m420.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-M420:
10 YUV 4:2:0. Hybrid plane line-interleaved layout.
22 directions. Each CbCr pair belongs to four pixels. For example,
30 Each cell is one byte.
33 .. flat-table::
34 :header-rows: 0
35 :stub-columns: 0
37 * - start + 0:
38 - Y'\ :sub:`00`
[all …]
/linux/Documentation/filesystems/spufs/
H A Dspufs.rst1 .. SPDX-License-Identifier: GPL-2.0
10 spufs - the SPU file system
16 The SPU file system is used on PowerPC machines that implement the Cell
26 logical SPU. Users can change permissions on those files, but not actu-
43 The files in spufs mostly follow the standard behavior for regular sys-
55 All files support the chmod(2)/fchmod(2) and chown(2)/fchown(2) opera-
81 The first SPU to CPU communication mailbox. This file is read-only and
82 can be read in units of 32 bits. The file can only be used in non-
87 If a count smaller than four is requested, read returns -1 and
89 box, the return value is set to -1 and errno becomes EAGAIN.
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
/linux/Documentation/devicetree/bindings/dma/stm32/
H A Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
[all …]
/linux/drivers/bus/
H A Dhisi_lpc.c1 // SPDX-License-Identifier: GPL-2.0+
22 #define DRV_NAME "hisi-lpc"
42 /* The max IO cycle counts supported is four per operation at maximum */
84 return (status & LPC_REG_OP_STATUS_FINISHED) ? 0 : -EIO; in wait_lpc_idle()
86 } while (--waitcnt); in wait_lpc_idle()
88 return -ETIMEDOUT; in wait_lpc_idle()
92 * hisi_lpc_target_in - trigger a series of LPC cycles for read operation
99 * Returns 0 on success, non-zero on fail.
110 if (!buf || !opcnt || !para || !para->csize || !lpcdev) in hisi_lpc_target_in()
111 return -EINVAL; in hisi_lpc_target_in()
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dusb-device.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps
17 Four types of device-tree nodes are defined: "host-controller nodes"
31 pattern: "^usb[0-9a-f]{1,4},[0-9a-f]{1,4}$"
41 description: the number of the USB hub port or the USB host-controller
42 port to which this device is attached. The range is 1-255.
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
8 * None of the four SerDes lanes are used by the module, instead they are
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
28 phy0: ethernet-phy@4 {
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dallwinner,sun6i-a31-msgbox.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Samuel Holland <samuel@sholland.org>
14 two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt
17 hold four 32-bit messages; when a FIFO is full, clients must wait before
20 Refer to ./mailbox.txt for generic information about mailbox device-tree
26 - items:
27 - enum:
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