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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
15 interface external sigma delta modulators to STM32 micro controllers.
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-adc-stm325 The STM32 ADC can be configured to use external trigger sources
7 conversions on external trigger by either:
9 - "rising-edge"
10 - "falling-edge"
11 - "both-edges".
H A Dsysfs-bus-counter3 Contact: linux-iio@vger.kernel.org
11 Contact: linux-iio@vger.kernel.org
13 Selects the external clock pin for phase counting mode of
16 MTCLKA-MTCLKB:
17 MTCLKA and MTCLKB pins are selected for the external
20 MTCLKC-MTCLKD:
21 MTCLKC and MTCLKD pins are selected for the external
26 Contact: linux-iio@vger.kernel.org
33 Contact: linux-iio@vger.kernel.org
39 Contact: linux-iio@vger.kernel.org
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/linux/sound/soc/ti/
H A Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
30 #include "edma-pcm.h"
31 #include "davinci-i2s.h"
33 #define DRV_NAME "davinci-i2s"
38 * - This driver supports the "Audio Serial Port" (ASP),
41 * - But it labels it a "Multi-channel Buffered Serial Port"
43 * backward-compatible, possibly explaining that confusion.
45 * - OMAP chips have a controller called McBSP, which is
48 * - Newer DaVinci chips have a controller called McASP,
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-stp-xway.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 peripheral controller used to drive external shift register cascades. At most
16 - John Crispin <john@phrozen.org>
20 pattern: "^gpio@[0-9a-f]+$"
23 const: lantiq,gpio-stp-xway
28 gpio-controller: true
30 "#gpio-cells":
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
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/linux/drivers/net/dsa/mv88e6xxx/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 * Raw timestamps are in units of 10-ns clock periods.
44 * Raw timestamps are in units of 8-ns clock periods.
59 * Raw timestamps are in units of 4-ns clock periods.
84 if (!chip->info->ops->avb_ops->tai_read) in mv88e6xxx_tai_read()
85 return -EOPNOTSUPP; in mv88e6xxx_tai_read()
87 return chip->info->ops->avb_ops->tai_read(chip, addr, data, len); in mv88e6xxx_tai_read()
92 if (!chip->info->ops->avb_ops->tai_write) in mv88e6xxx_tai_write()
93 return -EOPNOTSUPP; in mv88e6xxx_tai_write()
95 return chip->info->ops->avb_ops->tai_write(chip, addr, data); in mv88e6xxx_tai_write()
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa27x-udc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include "pxa-regs.h"
12 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
13 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
15 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
17 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
19 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
44 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
45 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
46 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
[all …]
/linux/Documentation/peci/
H A Dpeci.rst1 .. SPDX-License-Identifier: GPL-2.0-only
13 controller is acting as a PECI originator and the processor - as
15 PECI can be used in both single processor and multiple-processor based
20 instead it is a part of External Design Specification (EDS) for given
21 Intel CPU. External Design Specifications are usually not publicly
25 ---------
27 PECI Wire interface uses a single wire for self-clocking and data
28 transfer. It does not require any additional control lines - the
29 physical layer is a self-clocked one-wire bus signal that begins each
30 bit with a driven, rising edge from an idle near zero volts. The
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/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h192 #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GEN…
309 #define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete…
312 #define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete…
315 #define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete…
318 #define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete…
321 #define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete…
324 #define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete…
468 …grammable number of frames is counted.The counting starts / end at VSYNC rising edge or falling ed…
471 …grammable number of frames is counted.The counting starts / end at VSYNC rising edge or falling ed…
474 …grammable number of frames is counted.The counting starts / end at VSYNC rising edge or falling ed…
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs42l43.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 - $ref: dai-common.yaml#
26 - cirrus,cs42l43
31 vdd-p-supply:
35 vdd-a-supply:
39 vdd-d-supply:
43 vdd-io-supply:
[all …]
H A Dcirrus,cs42l42.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
13 The CS42L42 is a low-power audio codec designed for portable applications.
14 It provides a high-dynamic range, stereo DAC for audio playback and a mono
15 high-dynamic-range ADC for audio capture. There is an integrated headset
21 - cirrus,cs42l42
22 - cirrus,cs42l83
29 VP-supply:
[all …]
/linux/drivers/usb/gadget/udc/
H A Dpxa27x_udc.h1 // SPDX-License-Identifier: GPL-2.0+
4 * Intel PXA27x on-chip full speed USB device controller
28 #define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */
36 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
37 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
39 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
41 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
43 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
60 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
61 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
[all …]
/linux/drivers/gpio/
H A Dgpio-sch.c1 // SPDX-License-Identifier: GPL-2.0
35 * Document Number: 328195-001
55 if (gpio >= sch->resume_base) { in sch_gpio_offset()
56 gpio -= sch->resume_base; in sch_gpio_offset()
65 if (gpio >= sch->resume_base) in sch_gpio_bit()
66 gpio -= sch->resume_base; in sch_gpio_bit()
78 reg_val = !!(ioread8(sch->regs + offset) & BIT(bit)); in sch_gpio_reg_get()
92 reg_val = ioread8(sch->regs + offset); in sch_gpio_reg_set()
99 iowrite8(reg_val, sch->regs + offset); in sch_gpio_reg_set()
107 spin_lock_irqsave(&sch->lock, flags); in sch_gpio_direction_in()
[all …]
/linux/drivers/extcon/
H A Dextcon-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * extcon_gpio.c - Single-state GPIO extcon driver based on extcon class
12 #include <linux/devm-helpers.h>
13 #include <linux/extcon-provider.h>
24 * struct gpio_extcon_data - A simple GPIO-controlled extcon device state container.
29 * @gpiod: GPIO descriptor for this external connector.
30 * @extcon_id: The unique id of specific external connector.
52 state = gpiod_get_value_cansleep(data->gpiod); in gpio_extcon_work()
53 extcon_set_state_sync(data->edev, data->extcon_id, state); in gpio_extcon_work()
60 queue_delayed_work(system_power_efficient_wq, &data->work, in gpio_irq_handler()
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
18 stdout-path = "serial2:115200n8";
31 power_button: power-button {
32 compatible = "gpio-keys";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pwr_key_l>;
36 key-power {
40 debounce-interval = <100>;
[all …]
H A Drk3288-veyron-pinky.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "../cros-ec-sbs.dtsi"
14 compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
17 /delete-node/backlight-regulator;
18 /delete-node/panel-regulator;
19 /delete-node/emmc-pwrseq;
20 /delete-node/vcc18-lcd;
24 /delete-property/power-supply;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-kevin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Kevin Rev 6+ board device tree source
5 * Copyright 2016-2017 Google, Inc
8 /dts-v1/;
9 #include "rk3399-gru-chromebook.dtsi"
10 #include <dt-bindings/input/linux-event-codes.h>
13 * Kevin-specific things
21 compatible = "google,kevin-rev15", "google,kevin-rev14",
22 "google,kevin-rev13", "google,kevin-rev12",
23 "google,kevin-rev11", "google,kevin-rev10",
[all …]
H A Drk3399-hugsun-x99.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /dts-v1/;
3 #include <dt-bindings/pwm/pwm.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
20 stdout-path = "serial2:1500000n8";
23 clkin_gmac: external-gmac-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
26 clock-output-names = "clkin_gmac";
[all …]
H A Drk3399-nanopi4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * RK3399-based FriendlyElec boards device tree source
14 /dts-v1/;
15 #include <dt-bindings/input/linux-event-codes.h>
27 stdout-path = "serial2:1500000n8";
30 clkin_gmac: external-gmac-clock {
31 compatible = "fixed-clock";
32 clock-frequency = <125000000>;
33 clock-output-names = "clkin_gmac";
34 #clock-cells = <0>;
[all …]
/linux/drivers/comedi/drivers/
H A Damplc_pc236.c1 // SPDX-License-Identifier: GPL-2.0+
8 * COMEDI - Linux Control and Measurement Device Interface
19 * Configuration options - PC36AT:
20 * [0] - I/O port base address
21 * [1] - IRQ (optional)
27 * a rising edge on port C bit 3 acts as an external trigger, which can be
46 return -ENOMEM; in pc236_attach()
48 ret = comedi_request_region(dev, it->options[0], 0x4); in pc236_attach()
52 return amplc_pc236_common_attach(dev, dev->iobase, it->options[1], 0); in pc236_attach()
/linux/drivers/irqchip/
H A Dirq-pic32-evic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/mach-pic32/pic32.h>
53 return (struct evic_chip_data *)data->domain->host_data; in irqd_to_priv()
59 * External interrupts can be either edge rising or edge falling, in pic32_set_ext_polarity()
70 return -EINVAL; in pic32_set_ext_polarity()
84 return -EBADR; in pic32_set_type_edge()
86 /* set polarity for external interrupts only */ in pic32_set_type_edge()
87 for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) { in pic32_set_type_edge()
88 if (priv->ext_irqs[i] == data->hwirq) { in pic32_set_type_edge()
127 struct evic_chip_data *priv = d->host_data; in pic32_irq_domain_map()
[all …]
/linux/Documentation/hwmon/
H A Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
[all …]

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