1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/mach-pic32/pic32.h>
53 	return (struct evic_chip_data *)data->domain->host_data;  in irqd_to_priv()
59 	 * External interrupts can be either edge rising or edge falling,  in pic32_set_ext_polarity()
70 		return -EINVAL;  in pic32_set_ext_polarity()
84 		return -EBADR;  in pic32_set_type_edge()
86 	/* set polarity for external interrupts only */  in pic32_set_type_edge()
87 	for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {  in pic32_set_type_edge()
88 		if (priv->ext_irqs[i] == data->hwirq) {  in pic32_set_type_edge()
127 	struct evic_chip_data *priv = d->host_data;  in pic32_irq_domain_map()
143 	if (priv->irq_types[hw] & IRQ_TYPE_SENSE_MASK) {  in pic32_irq_domain_map()
145 		irqd_set_trigger_type(data, priv->irq_types[hw]);  in pic32_irq_domain_map()
146 		irq_setup_alt_chip(data, priv->irq_types[hw]);  in pic32_irq_domain_map()
168 	struct evic_chip_data *priv = d->host_data;  in pic32_irq_domain_xlate()
171 		return -EINVAL;  in pic32_irq_domain_xlate()
174 		return -EINVAL;  in pic32_irq_domain_xlate()
179 	priv->irq_types[intspec[0]] = intspec[1] & IRQ_TYPE_SENSE_MASK;  in pic32_irq_domain_xlate()
192 	struct evic_chip_data *priv = domain->host_data;  in pic32_ext_irq_of_init()
195 	const char *pname = "microchip,external-irqs";  in pic32_ext_irq_of_init()
198 		if (i >= ARRAY_SIZE(priv->ext_irqs)) {  in pic32_ext_irq_of_init()
199 			pr_warn("More than %d external irq, skip rest\n",  in pic32_ext_irq_of_init()
200 				ARRAY_SIZE(priv->ext_irqs));  in pic32_ext_irq_of_init()
204 		priv->ext_irqs[i] = hwirq;  in pic32_ext_irq_of_init()
222 		return -ENOMEM;  in pic32_of_init()
226 		ret = -ENOMEM;  in pic32_of_init()
234 		ret = -ENOMEM;  in pic32_of_init()
242 	 * "non-persistent" which are mapped here to level and edge  in pic32_of_init()
247 					     "evic-level", handle_level_irq,  in pic32_of_init()
260 		gc->reg_base = evic_base;  in pic32_of_init()
261 		gc->unused = 0;  in pic32_of_init()
269 		gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;  in pic32_of_init()
270 		gc->chip_types[0].handler		= handle_fasteoi_irq;  in pic32_of_init()
271 		gc->chip_types[0].regs.ack		= ifsclr;  in pic32_of_init()
272 		gc->chip_types[0].regs.mask		= iec;  in pic32_of_init()
273 		gc->chip_types[0].chip.name		= "evic-level";  in pic32_of_init()
274 		gc->chip_types[0].chip.irq_eoi		= irq_gc_ack_set_bit;  in pic32_of_init()
275 		gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;  in pic32_of_init()
276 		gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;  in pic32_of_init()
277 		gc->chip_types[0].chip.flags		= IRQCHIP_SKIP_SET_WAKE;  in pic32_of_init()
280 		gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;  in pic32_of_init()
281 		gc->chip_types[1].handler		= handle_edge_irq;  in pic32_of_init()
282 		gc->chip_types[1].regs.ack		= ifsclr;  in pic32_of_init()
283 		gc->chip_types[1].regs.mask		= iec;  in pic32_of_init()
284 		gc->chip_types[1].chip.name		= "evic-edge";  in pic32_of_init()
285 		gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;  in pic32_of_init()
286 		gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;  in pic32_of_init()
287 		gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;  in pic32_of_init()
288 		gc->chip_types[1].chip.irq_set_type	= pic32_set_type_edge;  in pic32_of_init()
289 		gc->chip_types[1].chip.flags		= IRQCHIP_SKIP_SET_WAKE;  in pic32_of_init()
291 		gc->private = &priv[i];  in pic32_of_init()
297 	 * External interrupts have software configurable edge polarity. These  in pic32_of_init()
317 IRQCHIP_DECLARE(pic32_evic, "microchip,pic32mzda-evic", pic32_of_init);