1*0580565dSIwona Winiarska.. SPDX-License-Identifier: GPL-2.0-only 2*0580565dSIwona Winiarska 3*0580565dSIwona Winiarska======== 4*0580565dSIwona WiniarskaOverview 5*0580565dSIwona Winiarska======== 6*0580565dSIwona Winiarska 7*0580565dSIwona WiniarskaThe Platform Environment Control Interface (PECI) is a communication 8*0580565dSIwona Winiarskainterface between Intel processor and management controllers 9*0580565dSIwona Winiarska(e.g. Baseboard Management Controller, BMC). 10*0580565dSIwona WiniarskaPECI provides services that allow the management controller to 11*0580565dSIwona Winiarskaconfigure, monitor and debug platform by accessing various registers. 12*0580565dSIwona WiniarskaIt defines a dedicated command protocol, where the management 13*0580565dSIwona Winiarskacontroller is acting as a PECI originator and the processor - as 14*0580565dSIwona Winiarskaa PECI responder. 15*0580565dSIwona WiniarskaPECI can be used in both single processor and multiple-processor based 16*0580565dSIwona Winiarskasystems. 17*0580565dSIwona Winiarska 18*0580565dSIwona WiniarskaNOTE: 19*0580565dSIwona WiniarskaIntel PECI specification is not released as a dedicated document, 20*0580565dSIwona Winiarskainstead it is a part of External Design Specification (EDS) for given 21*0580565dSIwona WiniarskaIntel CPU. External Design Specifications are usually not publicly 22*0580565dSIwona Winiarskaavailable. 23*0580565dSIwona Winiarska 24*0580565dSIwona WiniarskaPECI Wire 25*0580565dSIwona Winiarska--------- 26*0580565dSIwona Winiarska 27*0580565dSIwona WiniarskaPECI Wire interface uses a single wire for self-clocking and data 28*0580565dSIwona Winiarskatransfer. It does not require any additional control lines - the 29*0580565dSIwona Winiarskaphysical layer is a self-clocked one-wire bus signal that begins each 30*0580565dSIwona Winiarskabit with a driven, rising edge from an idle near zero volts. The 31*0580565dSIwona Winiarskaduration of the signal driven high allows to determine whether the bit 32*0580565dSIwona Winiarskavalue is logic '0' or logic '1'. PECI Wire also includes variable data 33*0580565dSIwona Winiarskarate established with every message. 34*0580565dSIwona Winiarska 35*0580565dSIwona WiniarskaFor PECI Wire, each processor package will utilize unique, fixed 36*0580565dSIwona Winiarskaaddresses within a defined range and that address should 37*0580565dSIwona Winiarskahave a fixed relationship with the processor socket ID - if one of the 38*0580565dSIwona Winiarskaprocessors is removed, it does not affect addresses of remaining 39*0580565dSIwona Winiarskaprocessors. 40*0580565dSIwona Winiarska 41*0580565dSIwona WiniarskaPECI subsystem internals 42*0580565dSIwona Winiarska------------------------ 43*0580565dSIwona Winiarska 44*0580565dSIwona Winiarska.. kernel-doc:: include/linux/peci.h 45*0580565dSIwona Winiarska.. kernel-doc:: drivers/peci/internal.h 46*0580565dSIwona Winiarska.. kernel-doc:: drivers/peci/core.c 47*0580565dSIwona Winiarska.. kernel-doc:: drivers/peci/request.c 48*0580565dSIwona Winiarska 49*0580565dSIwona WiniarskaPECI CPU Driver API 50*0580565dSIwona Winiarska------------------- 51*0580565dSIwona Winiarska.. kernel-doc:: drivers/peci/cpu.c 52