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/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_hal.c1 // SPDX-License-Identifier: GPL-2.0
12 * emu_enable_cores - Enable EMU cluster cores.
23 emu_ae.s.enable = 0xfffff; in emu_enable_cores()
27 emu_se.s.enable = 0xffff; in emu_enable_cores()
29 /* enable per cluster cores */ in emu_enable_cores()
37 * nitrox_config_emu_unit - configure EMU unit.
44 u64 offset; in nitrox_config_emu_unit() local
47 /* enable cores */ in nitrox_config_emu_unit()
50 /* enable general error and watch dog interrupts */ in nitrox_config_emu_unit()
58 offset = EMU_WD_INT_ENA_W1SX(i); in nitrox_config_emu_unit()
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/linux/sound/soc/sof/intel/
H A Dhda-ctrl.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
22 #include <sound/hda-mlink.h>
53 dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n", in hda_dsp_ctrl_link_reset()
55 return -EIO; in hda_dsp_ctrl_link_reset()
61 u32 cap, offset, featur in hda_dsp_ctrl_get_caps() local
133 hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev * sdev,bool enable) hda_dsp_ctrl_ppcap_enable() argument
142 hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev * sdev,bool enable) hda_dsp_ctrl_ppcap_int_enable() argument
151 hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev * sdev,bool enable) hda_dsp_ctrl_misc_clock_gating() argument
163 hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev * sdev,bool enable) hda_dsp_ctrl_clock_power_gating() argument
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/linux/drivers/gpu/drm/bridge/adv7511/
H A Dadv7511_cec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * adv7511_cec.c - Analog Devices ADV7511/33 cec driver
38 unsigned int offset = adv7511->info->reg_cec_offset; in adv_cec_tx_raw_status() local
41 if (regmap_read(adv7511->regmap_cec, in adv_cec_tx_raw_status()
42 ADV7511_REG_CEC_TX_ENABLE + offset, &val)) in adv_cec_tx_raw_status()
49 drm_connector_hdmi_cec_transmit_attempt_done(adv7511->cec_connector, in adv_cec_tx_raw_status()
65 if (regmap_read(adv7511->regmap_cec, in adv_cec_tx_raw_status()
66 ADV7511_REG_CEC_TX_LOW_DRV_CNT + offset, &cnt)) { in adv_cec_tx_raw_status()
77 drm_connector_hdmi_cec_transmit_done(adv7511->cec_connector, status, in adv_cec_tx_raw_status()
83 drm_connector_hdmi_cec_transmit_attempt_done(adv7511->cec_connector, in adv_cec_tx_raw_status()
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/linux/drivers/gpu/drm/radeon/
H A Devergreen_hdmi.c38 /* enable the audio stream */
69 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, in evergreen_hdmi_update_acr() argument
72 struct drm_device *dev = encoder->dev; in evergreen_hdmi_update_acr()
73 struct radeon_device *rdev = dev->dev_private; in evergreen_hdmi_update_acr()
76 if (encoder->crtc) { in evergreen_hdmi_update_acr()
77 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in evergreen_hdmi_update_acr()
78 bpc = radeon_crtc->bpc; in evergreen_hdmi_update_acr()
82 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
85 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
89 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
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/linux/include/linux/usb/
H A Dehci_def.h1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2001-2002 by David Brownell
9 #include <linux/usb/ehci-dbgp.h>
17 * some hosts treat caplength and hciversion as parts of a 32-bit
22 #define HC_LENGTH(ehci, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
24 #define HC_VERSION(ehci, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
26 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
34 #define HCS_N_PORTS_MAX 15 /* N_PORTS valid 0x1-0xF */
36 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
48 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
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/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dpm3393.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
39 #define OFFSET(REG_ADDR) ((REG_ADDR) << 2) macro
87 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
93 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
104 * Enable interrupts for the PM3393
106 * 1. Enable PM3393 BLOCK interrupts.
107 * 2. Enable PM3393 Master Interrupt bit(INTE)
108 * 3. Enable ELMER's PM3393 bit.
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/linux/drivers/mtd/nand/raw/
H A Domap_elm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #define DRIVER_NAME "omap-elm"
37 /* ELM Interrupt Enable Register */
50 /* ELM_ERROR_LOCATION_0-15 Registers */
85 static void elm_write_reg(struct elm_info *info, int offset, u32 val) in elm_write_reg() argument
87 writel(val, info->elm_base + offset); in elm_write_reg()
90 static u32 elm_read_reg(struct elm_info *info, int offset) in elm_read_reg() argument
92 return readl(info->elm_base + offset); in elm_read_reg()
96 * elm_config - Configure ELM module
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/linux/arch/powerpc/include/asm/
H A Dreg_booke.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright 2009-2010 Freescale Semiconductor, Inc.
12 #include <asm/ppc-opcode.h>
16 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
17 #define MSR_SPE_LG 25 /* Enable SPE */
18 #define MSR_DWE_LG 10 /* Debug Wait Enable */
19 #define MSR_UBLE_LG 10 /* BTB lock enable (e500) */
23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
87 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
88 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
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/linux/drivers/net/ethernet/cortina/
H A Dgemini.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
51 * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
170 /* DMA Queues description Ring Base Address/Size Register (offset 0x0004) */
178 /* DMA SKB Buffer register (offset 0x0008) */
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/linux/drivers/media/platform/imagination/
H A De5010-jpeg-enc-hw.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
7 * Author: David Huang <d-huang@ti.com>
14 #include "e5010-jpeg-enc-hw.h"
16 static void write_reg_field(void __iomem *base, unsigned int offset, u32 mask, in write_reg_field() argument
23 reg = readl(base + offset); in write_reg_field()
26 writel(value, (base + offset)); in write_reg_field()
30 unsigned int offset, u32 mask, unsigned int shift, in write_reg_field_not_busy() argument
42 write_reg_field(wr_base, offset, mask, shift, value); in write_reg_field_not_busy()
71 void e5010_hw_bypass_mmu(void __iomem *mmu_base, u32 enable) in e5010_hw_bypass_mmu() argument
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/linux/drivers/net/wan/
H A Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
32 #define IER0 0x14 /* Interrupt Enable 0 */
33 #define IER1 0x15 /* Interrupt Enable 1 */
34 #define IER2 0x16 /* Interrupt Enable 2 */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
55 #define IE0 0x08 /* Interrupt Enable 0 */
56 #define IE1 0x09 /* Interrupt Enable 1 */
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/linux/drivers/rtc/
H A Drtc-snvs.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
46 int offset; member
56 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb); in rtc_read_lpsrt()
57 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb); in rtc_read_lpsrt()
78 diff = read1 - read2; in rtc_read_lp_counter()
79 } while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout); in rtc_read_lp_counter()
81 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n"); in rtc_read_lp_counter()
83 /* Convert 47-bit counter to 32-bit raw second count */ in rtc_read_lp_counter()
94 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); in rtc_read_lp_counter_lsb()
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/linux/drivers/regulator/
H A Dpbias-regulator.c2 * pbias-regulator.c
4 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
30 u32 enable; member
41 unsigned int offset; member
58 .enable = regulator_enable_regmap,
64 .enable = BIT(1),
75 .enable = BIT(9),
85 .enable = BIT(26) | BIT(22),
96 .enable = BIT(27) | BIT(26),
114 /* Offset from SCM general area (and syscon) base */
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/linux/Documentation/trace/
H A Duprobetracer.rst2 Uprobe-tracer: Uprobe-based Event Tracing
9 --------
11 To enable this feature, build your kernel with CONFIG_UPROBE_EVENTS=y.
13 Similar to the kprobe-event tracer, this doesn't need to be activated via
15 /sys/kernel/tracing/uprobe_events, and enable it via
16 /sys/kernel/tracing/events/uprobes/<EVENT>/enable.
18 However unlike kprobe-event tracer, the uprobe event interface expects the
19 user to calculate the offset of the probepoint in the object.
26 -------------------------
29 p[:[GRP/][EVENT]] PATH:OFFSET [FETCHARGS] : Set a uprobe
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-adc-mcp35643 Contact: linux-iio@vger.kernel.org
6 circuit of the Delta-Sigma modulator. The different BOOST
12 Contact: linux-iio@vger.kernel.org
15 the current biasing circuit of the Delta-Sigma modulator.
19 Contact: linux-iio@vger.kernel.org
21 This attribute is used to enable the analog input multiplexer
22 auto-zeroing algorithm (the input multiplexer and the ADC
23 include an offset cancellation algorithm that cancels the offset
24 contribution of the ADC). When the offset cancellation algorithm
26 input as VIN+/VIN-, one with VIN+/VIN- inverted. In this case the
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/linux/drivers/pinctrl/
H A Dpinctrl-at91.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
12 #define PIO_PER 0x00 /* Enable Register */
15 #define PIO_OER 0x10 /* Output Enable Register */
18 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */
25 #define PIO_IER 0x40 /* Interrupt Enable Register */
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
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/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dlmac_common.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct lmac - per lmac locks and properties
58 * bar offset for example
70 /* lmac offset is different is RPM */
79 /* Unlike CN10K which shares same CSR offset with CGX
80 * CNF10KB has different csr offset
91 bool enable);
98 /* Enable LMAC Pause Frame Configuration */
101 bool enable);
115 bool enable);
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/linux/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
10 0: POFF--Power Off
11 1: PDN--Power Down
12 2: CARDEMU--Card Emulation
13 3: ACT--Active Mode
14 4: LPS--Low Power State
15 5: SUS--Suspend
41 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
42 …SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block…
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/linux/drivers/clk/bcm/
H A Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
16 #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
18 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
21 #define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
24 { .offset = o, .en_shift = es, .high_shift = hs, \
27 #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
30 #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
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H A Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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H A Dclk-iproc-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
103 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
104 vco_out->pdiv = 1; in pll_calc_param()
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/linux/drivers/net/ipa/
H A Dipa_interrupt.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2024 Linaro Ltd.
36 * struct ipa_interrupt - IPA interrupt information
52 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_suspend_clear_all()
56 unit_count = DIV_ROUND_UP(ipa->endpoint_count, 32); in ipa_interrupt_suspend_clear_all()
62 val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit)); in ipa_interrupt_suspend_clear_all()
65 if (!val || ipa->version == IPA_VERSION_3_0) in ipa_interrupt_suspend_clear_all()
69 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, unit)); in ipa_interrupt_suspend_clear_all()
76 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_process()
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/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
56 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
57 #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
85 #define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
107 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
136 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dpwrseq.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
9 * Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
11 * 0: POFF--Power Off
12 * 1: PDN--Power Down
13 * 2: CARDEMU--Card Emulation
14 * 3: ACT--Active Mode
15 * 4: LPS--Low Power State
16 * 5: SUS--Suspend
42 /* {offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value}, */\
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/linux/drivers/net/wwan/t7xx/
H A Dt7xx_pcie_mac.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2021-2022, Intel Corporation.
20 #include <linux/io-64-nonatomic-lo-hi.h>
73 int i, offset; in t7xx_pcie_mac_atr_tables_dis() local
76 offset = ATR_PORT_OFFSET * port + ATR_TABLE_OFFSET * i; in t7xx_pcie_mac_atr_tables_dis()
77 reg = pbase + ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR + offset; in t7xx_pcie_mac_atr_tables_dis()
84 struct device *dev = &t7xx_dev->pdev->dev; in t7xx_pcie_mac_atr_cfg()
86 int atr_size, pos, offset; in t7xx_pcie_mac_atr_cfg() local
90 if (cfg->transparent) { in t7xx_pcie_mac_atr_cfg()
94 if (cfg->src_addr & (cfg->size - 1)) { in t7xx_pcie_mac_atr_cfg()
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