Lines Matching +full:enable +full:- +full:offset
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
22 #include <sound/hda-mlink.h>
53 dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",
55 return -EIO;
61 u32 cap, offset, feature;
76 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
79 dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
80 offset & SOF_HDA_CAP_NEXT_MASK);
82 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
84 if (cap == -1) {
85 dev_dbg(bus->dev, "Invalid capability reg read\n");
93 dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
94 offset);
95 bus->ppcap = bus->remap_addr + offset;
96 sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
99 dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
100 offset);
101 bus->spbcap = bus->remap_addr + offset;
102 sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
105 dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
106 offset);
107 bus->drsmcap = bus->remap_addr + offset;
108 sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
111 dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
112 offset);
113 bus->gtscap = bus->remap_addr + offset;
116 dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
117 offset);
118 bus->mlcap = bus->remap_addr + offset;
121 dev_dbg(sdev->dev, "found capability %d at 0x%x\n",
122 feature, offset);
126 offset = cap & SOF_HDA_CAP_NEXT_MASK;
127 } while (count++ <= SOF_HDA_MAX_CAPS && offset);
133 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
135 u32 val = enable ? SOF_HDA_PPCTL_GPROCEN : 0;
142 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
144 u32 val = enable ? SOF_HDA_PPCTL_PIE : 0;
151 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
153 u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0;
159 * enable/disable audio dsp clock gating and power gating bits.
163 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
165 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
168 /* enable/disable audio dsp clock gating */
169 val = enable ? PCI_CGCTL_ADSPDCGE : 0;
172 /* disable the DMI link when requested. But enable only if it wasn't disabled previously */
173 val = enable ? HDA_VS_INTEL_EM2_L1SEN : 0;
174 if (!enable || !hda->l1_disabled)
178 /* enable/disable audio dsp power gating */
179 val = enable ? 0 : PCI_PGCTL_ADSPPGD;
193 if (bus->chip_init)
209 dev_err(sdev->dev, "error: failed to reset HDA controller\n");
218 dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
230 list_for_each_entry(stream, &bus->stream_list, list) {
239 bus->codec_mask);
249 /* enable CIE and GIE interrupts */
255 if (bus->use_posbuf && bus->posbuf.addr) {
257 (u32)bus->posbuf.addr);
259 upper_32_bits(bus->posbuf.addr));
264 bus->chip_init = true;
281 if (!bus->chip_init)
285 list_for_each_entry(stream, &bus->stream_list, list) {
304 list_for_each_entry(stream, &bus->stream_list, list) {
324 if (bus->use_posbuf && bus->posbuf.addr) {
331 bus->chip_init = false;