Lines Matching +full:enable +full:- +full:offset
1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright 2009-2010 Freescale Semiconductor, Inc.
12 #include <asm/ppc-opcode.h>
16 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
17 #define MSR_SPE_LG 25 /* Enable SPE */
18 #define MSR_DWE_LG 10 /* Debug Wait Enable */
19 #define MSR_UBLE_LG 10 /* BTB lock enable (e500) */
23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
87 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
88 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
89 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
90 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
91 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
92 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
93 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
94 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
95 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
96 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
97 #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
98 #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
99 #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
100 #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
101 #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
102 #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
103 #define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */
104 #define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
105 #define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
106 #define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
107 #define SPRN_IVOR42 0x1B4 /* Interrupt Vector Offset Register 42 */
123 #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
124 #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
125 #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
126 #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
127 #define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
128 #define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
160 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
161 #define SPRN_SLER 0x3BB /* Little-endian real mode */
197 #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
201 #define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
204 #define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */
214 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
215 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
216 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
226 #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
229 #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
230 #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
241 #define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */
243 #define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */
262 #define HID1_RFXE 0x00020000 /* Read fault exception enable */
263 #define HID1_R1DPE 0x00008000 /* R1 data bus parity enable */
264 #define HID1_R2DPE 0x00004000 /* R2 data bus parity enable */
265 #define HID1_ASTME 0x00002000 /* Address bus streaming mode enable */
266 #define HID1_ABE 0x00001000 /* Address broadcast enable */
267 #define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */
294 #define ESR_MCI 0x80000000 /* Machine Check - Instruction */
295 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
296 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
297 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
298 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
299 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
300 #define ESR_PPR 0x04000000 /* Program Exception - Privileged */
301 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
303 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
304 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
328 #define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */
329 #define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */
330 #define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */
331 #define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */
332 #define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */
333 #define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */
334 #define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */
335 #define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */
341 #define dbcr_dac(task) ((task)->thread.debug.dbcr0)
358 #define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
359 #define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
360 #define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
371 #define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
372 #define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
373 #define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
375 #define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
378 #define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
381 #define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */
388 #define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
389 #define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/
390 #define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
391 #define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */
392 #define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
427 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
428 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
429 #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
436 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
437 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
447 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
463 #define DCWR_COPY 0 /* Copy-back */
464 #define DCWR_WRITE 1 /* Write-through */
471 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
476 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
479 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
482 #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
491 #define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
495 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
496 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
573 #define SPRN_TENSR 0x1b5 /* Thread Enable Status Register */
574 #define SPRN_TENS 0x1b6 /* Thread Enable Set Register */
575 #define SPRN_TENC 0x1b7 /* Thread Enable Clear Register */