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/linux/drivers/mmc/host/
H A Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
44 static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample) in rockchip_mmc_get_internal_phase() argument
46 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_get_internal_phase()
51 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_internal_phase()
55 if (sample) in rockchip_mmc_get_internal_phase()
76 static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) in rockchip_mmc_get_phase() argument
78 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()
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/linux/Documentation/devicetree/bindings/mmc/
H A Dhisilicon,hi3798cv200-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
26 - description: bus interface unit clock
27 - description: card interface unit clock
28 - description: card input sample phase clock
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/linux/drivers/iio/resolver/
H A Dad2s1210.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2010 Analog Devices Inc.
11 * ----------------------------|------|-------------------------------------------
20 * Phase lock range | D5 | events/in_phase0_mag_rising_value
23 * Resolution | D1:0 | *device tree: assigned-resolution-bits*
34 * ----------------------------------------|----|---------------------------------
41 * Phase error exceeds phase lock range | D1 | phase0 | mag | rising
143 /** GPIO pin connected to SAMPLE line. */
153 /* adi,fixed-mode property - only valid when mode_gpios == NULL. */
159 /** For reading raw sample value via SPI. */
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/linux/Documentation/networking/
H A Dcan.rst2 SocketCAN - Controller Area Network
20 .. _socketcan-motivation:
29 functionality. Usually, there is only a hardware-specific device
32 Queueing of frames and higher-level transport protocols like ISO-TP
34 character-device implementations support only one single process to
47 protocol family module and also vice-versa. Also, the protocol family
57 communicate using a specific transport protocol, e.g. ISO-TP, just
60 CAN-IDs, frames, etc.
62 Similar functionality visible from user-space could be provided by a
74 * **Abstraction:** In most existing character-device implementations, the
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/linux/drivers/iio/adc/
H A Dad7944.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #include <linux/iio/buffer-dmaengine.h>
40 /* datasheet calls this "4-wire mode" */
42 /* datasheet calls this "3-wire mode" (not related to SPI_3WIRE!) */
48 /* maps adi,spi-mode property value to enum */
67 /* Chip-specific timing specifications. */
73 /* Indicates TURBO is hard-wired to be always enabled. */
88 } sample __aligned(IIO_DMA_MINALIGN);
118 * AD7944_DEFINE_CHIP_INFO - Define a chip info structure for a specific chip
121 * @_max: The maximum sample rate in Hz
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/linux/drivers/clk/rockchip/
H A Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
43 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
56 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
60 if (mmc_clock->grf) in rockchip_mmc_get_phase()
61 regmap_read(mmc_clock->grf, mmc_clock->grf_reg, &raw_value); in rockchip_mmc_get_phase()
63 raw_value = readl(mmc_clock->reg); in rockchip_mmc_get_phase()
65 raw_value >>= mmc_clock->shift; in rockchip_mmc_get_phase()
93 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
105 return -EINVAL; in rockchip_mmc_set_phase()
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/linux/Documentation/driver-api/media/drivers/
H A Dcx88-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
9 -------------------------------------------
13 .. code-block:: none
15 Previous default from DScaler: 0x1c1f0008
16 Digit 8: 31-28
19 Digit 7: 27-24 (0xc = 12 = b1100 )
24 Digits 6,5: 23-16
25 25-16: COMB_RANGE = 0x1f [default] (9 bits -> max 512)
27 Digit 4: 15-12
33 Digit 3: 11-8
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/linux/arch/arm/boot/dts/rockchip/
H A Drv1126-sonoff-ihost.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 stdout-path = "serial2:1500000n8";
19 vcc5v0_sys: regulator-vcc5v0-sys {
20 compatible = "regulator-fixed";
21 regulator-name = "vcc5v0_sys";
22 regulator-always-on;
23 regulator-boot-on;
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
28 sdio_pwrseq: pwrseq-sdio {
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H A Drk3288-veyron-sdmmc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
15 sdcard-supply = <&vccio_sd>;
24 sdmmc_bus4: sdmmc-bus4 {
31 sdmmc_clk: sdmmc-clk {
35 sdmmc_cmd: sdmmc-cmd {
45 sdmmc_cd_disabled: sdmmc-cd-disabled {
50 sdmmc_cd_pin: sdmmc-cd-pin {
57 vcc9-supply = <&vcc_5v>;
61 regulator-name = "vccio_sd";
62 regulator-min-microvolt = <1800000>;
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/linux/drivers/iio/dac/
H A Dadi-axi-dac.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2016-2024 Analog Devices Inc.
26 #include <linux/fpga/adi-axi-common.h>
28 #include <linux/iio/buffer-dmaengine.h>
32 #include "ad3552r-hs.h"
127 guard(mutex)(&st->lock); in axi_dac_enable()
128 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
137 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, in axi_dac_enable()
144 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
152 guard(mutex)(&st->lock); in axi_dac_disable()
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/linux/tools/testing/selftests/ptp/
H A Dtestptp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock support - User space test program
35 #define CLOCK_INVALID -1
113 return t->sec * NSEC_PER_SEC + t->nsec; in pctns()
120 " -c query the ptp clock's capabilities\n" in usage()
121 " -d name device to open\n" in usage()
122 " -e val read 'val' external time stamp events\n" in usage()
123 " -f val adjust the ptp clock frequency by 'val' ppb\n" in usage()
124 " -F chan Enable single channel mask and keep device open for debugfs verification.\n" in usage()
125 " -g get the ptp clock time\n" in usage()
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/linux/Documentation/trace/rv/
H A Dda_monitor_instrumentation.rst51 --------------------------
84 Otherwise, the monitor and the system could be out-of-sync.
113 ----------------------------
132 But no change was required because: by default, these functions *attach* and
136 -----------------------
139 kernel event, at the monitoring enable phase.
143 adds "rv_attach_trace_probe()" function call for each model event in the enable phase, as
146 For example, from the wip sample model::
163 The probes then need to be detached at the disable phase.
/linux/net/ipv4/
H A Dtcp_bbr.c21 * +---> STARTUP ----+
24 * | DRAIN ----+
27 * +---> PROBE_BW ----+
30 * | +----+ |
32 * +---- PROBE_RTT <--+
37 * A long-lived BBR flow spends the vast majority of its time remaining
41 * sample that matches or decreases its min_rtt estimate for 10 seconds, then
42 * it briefly enters PROBE_RTT to cut inflight to a minimum value to re-probe
43 * the path's two-way propagation delay (min_rtt). When exiting PROBE_RTT, if
48 * "BBR: Congestion-Based Congestion Control",
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H A Dtcp_westwood.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TCP Westwood+: end-to-end bandwidth estimation for TCP
10 * - Mascolo S, Casetti, M. Gerla et al.
13 * - A. Grieco, s. Mascolo
17 * - A. Dell'Aera, L. Grieco, S. Mascolo.
18 * "Linux 2.4 Implementation of Westwood+ TCP with Rate-Halving :
21 * Westwood+ employs end-to-end bandwidth measurement to set cwnd and
22 * ssthresh after packet loss. The probing phase is as the original Reno.
43 u8 reset_rtt_min; /* Reset RTT min to next RTT sample*/
65 w->bk = 0; in tcp_westwood_init()
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H A Dtcp_veno.c1 // SPDX-License-Identifier: GPL-2.0-only
20 /* Default values of the Veno variables, in fixed-point representation
36 /* There are several situations when we must "re-start" Veno:
50 veno->doing_veno_now = 1; in veno_enable()
52 veno->minrtt = 0x7fffffff; in veno_enable()
60 veno->doing_veno_now = 0; in veno_disable()
67 veno->basertt = 0x7fffffff; in tcp_veno_init()
68 veno->inc = 1; in tcp_veno_init()
74 const struct ack_sample *sample) in tcp_veno_pkts_acked() argument
79 if (sample->rtt_us < 0) in tcp_veno_pkts_acked()
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/linux/tools/perf/scripts/python/
H A Dgecko.py1 # gecko.py - Convert perf record output to Firefox's gecko profile format
2 # SPDX-License-Identifier: GPL-2.0
9 # perf record -a -g -F 99 sleep 60
14 # perf script gecko -F 99 -a sleep 60
32 # Add the Perf-Trace-Util library to the Python path
34 '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
48 # https://github.com/firefox-devtools/profiler/blob/53970305b51b9b472e26d7457fee1d66cd4e2737/src/ty…
49 …llow Brendan Gregg's Flamegraph convention: orange for kernel and yellow for user space by default.
53 PRODUCT = os.popen('uname -op').read().strip()
68 # https://github.com/firefox-devtools/profiler/blob/53970305b51b9b472e26d7457fee1d66cd4e2737/src/ty…
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/linux/include/sound/
H A Demu10k1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
41 // This is used to define hardware bit-fields (sub-registers) by combining
44 // The non-concatenating (_NC) variant should be used directly only for
45 // sub-registers that do not follow the <register>_<field> naming pattern.
55 // Macros for manipulating values of bit-fields declared using the above macros.
59 // single sub-register at a time.
62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
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H A Dcs8427.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */
34 #define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */
40 #define CS8427_SWCLK (1<<7) /* 0 = RMCK default, 1 = OMCK output on RMCK pin */
52 #define CS8427_HOLDLASTSAMPLE (0<<5) /* hold the last valid sample */
53 #define CS8427_HOLDZERO (1<<5) /* replace the current audio sample with zero (mute) */
54 #define CS8427_HOLDNOCHANGE (2<<5) /* do not change the received audio sample */
63 #define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
65 #define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */
66 #define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */
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/linux/tools/lib/bpf/
H A Dlibbpf.h1 /* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */
6 * Copyright (C) 2013-2015 Alexei Starovoitov <ast@kernel.org>
100 * @brief **libbpf_set_print()** sets user-provided log callback function to
102 * is not set, messages are logged to stderr by default. The verbosity of these
108 * This function is thread-safe.
119 * - fo
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_audio.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
35 aud->base.ctx
40 (aud->regs->reg)
44 aud->shifts->field_name, aud->masks->field_name
99 for (index = 0; index < audio_info->mode_count; index++) { in is_audio_format_supported()
100 if (audio_info->modes[index].format_code == audio_format_code) { in is_audio_format_supported()
104 if (audio_info->modes[index].channel_count > in is_audio_format_supported()
105 audio_info->modes[max_channe_index].channel_count) { in is_audio_format_supported()
123 /*For HDMI, calculate if specified sample rates can fit into a given timing */
142 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && in check_audio_bandwidth_hdmi()
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/linux/tools/perf/Documentation/
H A Dperf-top.txt1 perf-top(1)
5 ----
6 perf-top - System profiling tool.
9 --------
11 'perf top' [-e <EVENT> | --event=EVENT] [<options>]
14 -----------
19 -------
20 -a::
21 --all-cpus::
22 System-wide collection. (default)
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/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
64 * (Default 0)
71 * 0: Encode (TW5864 Default)
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
99 /* Org Buffer Base for Luma (default 0) */
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/linux/Documentation/dev-tools/
H A Dpropeller.rst1 .. SPDX-License-Identifier: GPL-2.0
8 compiler. Propeller is a profile-guided optimization (PGO) method used
12 is then used right before linking phase to optimize (among others)
24 "build-afdo - train-afdo - build-propeller - train-propeller -
25 build-optimized".
37 you would normally do, but with a set of compile-time / link-time
54 binary as you would normally do, but with a compile-time /
55 link-time flag to pick up the Propeller compile time and link time
56 profiles. This build step uses 3 profiles - the AutoFDO profile,
57 the Propeller compile-time profile and the Propeller link-time
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/linux/drivers/mfd/
H A Dcs47l24-tables.c1 // SPDX-License-Identifier: GPL-2.0-only
29 return regmap_register_patch(arizona->regmap, in cs47l24_patch()
183 { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
184 { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
185 { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
186 { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
187 { 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
188 { 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
189 { 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
190 { 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
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/linux/drivers/spi/
H A Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/spi/spi-mem.h>
23 #include "spi-dw.h"
32 u32 rx_sample_dly; /* RX sample delay */
66 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
67 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
69 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
70 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
71 dws->regset.base = dws->regs; in dw_spi_debugfs_init()
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