Lines Matching +full:default +full:- +full:sample +full:- +full:phase
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
64 * (Default 0)
71 * 0: Encode (TW5864 Default)
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
99 /* Org Buffer Base for Luma (default 0) */
101 /* Org Buffer Base for Chroma (default 4) */
103 /* Maximum Number of Buffers (default 4) */
107 * (Default 0)
113 /* Ref Buffer Base for Luma (default 0) */
115 /* Ref Buffer Base for Chroma (default 4) */
117 /* Maximum Number of Buffers (default 4) */
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
196 * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
203 * De-interlacer Mode
205 * 0 Normal Un-Shuffled Frame
210 * 11: Un-used
211 * 10: down-sample to 1/4
212 * 01: down-sample to 1/2
213 * 00: down-sample disabled
218 * 11: Un-used
219 * 10: down-sample to 1/4
220 * 01: down-sample to 1/2
221 * 00: down-sample disabled
232 /* Number of reference frame (Default 1 for TW5864B) */
241 * 0 DSP_SKIP_OFFSET value is not used (default 8)
245 /* Skip mode cost offset (default 8) */
260 /* Search Option (Default 2"b01) */
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
422 * Swap byte order of VLC stream in d-word.
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
691 * 2'b00 phase set to 180 degree
692 * 2'b01 phase set to 270 degree
693 * 2'b10 phase set to 0 degree
694 * 2'b11 phase set to 90 degree
699 * The system / DDR clock (166 MHz) is generated with an on-chip system clock
729 * 0 Lower current (default)
765 * 1 6.6K ohms (default)
773 * 00 x1 (default)
780 * PLL low pass filter phase margin adjustment
781 * 0 no 5pF (default)
787 * 0 Falling edge (default)
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
848 * 1 High level or pos-edge is assertion
849 * 0 Low level or neg-edge is assertion
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
935 * 0 Interlaced (TW5864 default)
992 * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1025 * default is 7
1030 * default is 4"hf
1036 * period, default is 4"h2
1040 /* Twr value, write recovery time, default is 4"h3 */
1046 * availability of the first bit of output data, default is 3
1068 * 1 DDR self-test mode
1072 * 0 DDR self-test single read/write
1073 * 1 DDR self-test burst read/write
1077 * 0 DDR self-test write command
1078 * 1 DDR self-test read command
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1115 /* [15:0] Default is C013 */
1120 /* Audio data in to DDR enable (default 1) */
1122 /* Audio encode request to DDR enable (default 1) */
1124 /* Audio decode request0 to DDR enable (default 1) */
1126 /* Audio decode request1 to DDR enable (default 1) */
1128 /* VLC stream request to DDR enable (default 1) */
1130 /* H264 MV request to DDR enable (default 1) */
1132 /* mux_core MVD request to DDR enable (default 1) */
1134 /* mux_core MVD temp data request to DDR enable (default 1) */
1136 /* JPEG request to DDR enable (default 1) */
1138 /* mv_flag request to DDR enable (default 1) */
1143 /* ARB12 Enable (default 1) */
1145 /* ARB12 maximum value of time out counter (default 15"h1FF) */
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1312 * Every channel of preview and audio have ping-pong buffers in system memory,
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1411 /* Length of 32-bit data burst */
1444 /* 0x84000 - 0x87ffc */
1454 /* Read-only register */
1469 * 1 Sub-carrier PLL is locked to the incoming video source.
1470 * 0 Sub-carrier PLL is not locked.
1497 /* VCR signal indicator. Read-only. */
1499 /* Weak signal indicator 2. Read-only. */
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1505 * 0 = Non-standard signal
1506 * Read-only
1510 * 1 = Non-interlaced signal
1512 * Read-only
1517 * 0 = None (default)
1542 * active pixel for display / record path. A unit is 1 pixel. The default value
1546 * for display / record path. A unit is 1 pixel. The default value is decimal
1550 * active for display / record path. A unit is 1 line. The default value is
1554 * for display / record path. A unit is 1 line. The default value is decimal
1559 * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1561 * purplish tone. The default value is 0o (00h). This is effective only on NTSC
1562 * system. The default is 00h.
1575 /* CTI level selection. The default is 1.
1586 * strongest. The default is 1.
1593 * default is 64h.
1598 * These bits control the brightness. They have value of -128 to 127 in 2's
1600 * effect on the data. The default is 00h.
1610 * gain of 100%. The default is 80h.
1620 * gain of 100%. The default is 80h.
1624 /* Read-only */
1627 /* Macrovision color stripe detection may be un-reliable */
1641 /* Read-only */
1645 * Read-only.
1667 * (Default)
1679 * 7 Auto detection (Default)
1687 * process. This bit is a self-clearing bit
1688 * 0 Manual initiation of auto format detection is done. (Default)
1691 /* Enable recognition of PAL60 (Default) */
1693 /* Enable recognition of PAL (CN). (Default) */
1695 /* Enable recognition of PAL (M). (Default) */
1697 /* Enable recognition of NTSC 4.43. (Default) */
1699 /* Enable recognition of SECAM. (Default) */
1701 /* Enable recognition of PAL (B, D, G, H, I). (Default) */
1703 /* Enable recognition of NTSC (M). (Default) */
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1727 * 8 1.00 (default)
1746 * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1747 * 0 PCM output (default)
1749 * 2 u-Law output
1750 * 3 A-Law output
1756 * 0 Apply individual mixing ratio value for each audio (default)
1765 * 1 Muted (default)
1774 * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1782 * 0 Not inversed (Default)
1788 * 0 Not inversed (Default)
1801 * 0 8kHz setting (Default)
1813 * 0 L/R half length separated output (Default).
1819 * 0 High periods is one 27MHz clock period (default).
1820 * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1841 * 0 No delay (Default). This is for I2S type 1T delay input interface.
1842 * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1847 * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1848 * 0 PCM input (Default)
1850 * 2 u-Law input
1851 * 3 A-Law input
1882 * Interrupt status register from the front-end. Write "1" to each bit to clear
1933 * 0 Enable motion and blind detection (default)
1939 * 0 None Operation (default)
1945 * 0 Automatic trigger mode of motion detection (default)
1951 * 0 Low threshold (More sensitive) (default)
1961 * 0 More Sensitive (default)
1969 * 0 0 pixel (default)
1979 * 0 Update reference field every field (default)
1985 * 0 Detecting motion for only odd field (default)
1994 * 0 More sensitive (default)
2003 * Define the threshold of sub-cell number for motion detection.
2004 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005 * 1 Motion is detected if 2 sub-cells have motion
2006 * 2 Motion is detected if 3 sub-cells have motion
2007 * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)
2015 * 0 1 field intervals (default)
2028 * 0 More Sensitive (default)
2036 * 0 Low threshold (More sensitive) (default)
2045 * 0 Low threshold (More sensitive) (default)
2053 * 0 Low threshold (More sensitive) (default)
2062 * 16"h0000}. The default value should be 12"h000