| /freebsd/sys/amd64/pci/ |
| H A D | pci_cfgreg.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 #include <sys/bus.h> 52 static uint32_t pci_docfgregread(int domain, int bus, int slot, int func, 54 static struct pcie_mcfg_region *pcie_lookup_region(int domain, int bus); 55 static int pciereg_cfgread(struct pcie_mcfg_region *region, int bus, 57 static void pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus, 58 unsigned slot, unsigned func, unsigned reg, int data, 60 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); [all …]
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| /freebsd/share/man/man9/ |
| H A D | bus_space.9 | 19 .\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 47 .\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 143 .Nd "bus space manipulation functions" 627 machine-independent access to bus memory and register areas. 640 creating a non-linear register space). 648 object file to manipulate a set of devices on multiple bus types on a 653 supported by the bus. 655 compile-time errors if possible. 661 (type-checked) versions of these interfaces, but may implement them as 663 Machine-dependent types, variables, and functions [all …]
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| H A D | own.9 | 18 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 .Nd Dallas Semiconductor 1-Wire Network and Transport Interface 66 interface defines three sets of functions for interacting with 1-Wire 69 reserving the bus, 71 ensuring data integrity. 78 .Ss Bus Commands 79 The 1-Wire bus defines different layers of access to the devices on 80 the bus. 85 devices on the bus, or for a specific device. 90 It specifies the commands to send and whether or not to read data. [all …]
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| /freebsd/share/man/man4/ |
| H A D | iicbus.4 | 19 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 .Nd I2C bus system 41 system provides a uniform, modular and architecture-independent 45 I2C is an acronym for Inter Integrated Circuit bus. 46 The I2C bus was developed 49 easy way to connect a CPU to peripheral chips in a TV-set. 51 The BUS physically consists of 2 active wires and a ground connection. 54 Serial DAta line and SCL is the Serial CLock line. 56 Every component hooked up to the bus has its own unique address whether it 63 more BUS MASTERs. [all …]
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| H A D | spigen.4 | 21 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 .Bd -ragged -offset indent 45 .Bd -literal -offset indent 51 driver provides direct access to a slave device on the SPI bus. 54 device is associated with a single chip-select 55 line on the bus, and all I/O performed through that instance is done 56 with that chip-select line asserted. 58 SPI data transfers are inherently bi-directional; there are no separate 60 When commands and data are sent to a device, data also comes back from 61 the device, although in some cases the data may not be useful (or even [all …]
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| /freebsd/sys/i386/pci/ |
| H A D | pci_cfgreg.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 #include <sys/bus.h> 84 "Enable support for PCI-e memory mapped config access"); 86 static uint32_t pci_docfgregread(int domain, int bus, int slot, int func, 88 static struct pcie_mcfg_region *pcie_lookup_region(int domain, int bus); 89 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); 90 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); 92 static int pciereg_cfgread(struct pcie_mcfg_region *region, int bus, [all …]
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| /freebsd/sys/dev/hid/ |
| H A D | hidbus.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2019-2020 Vladimir Kondratyev <wulf@FreeBSD.org> 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 #include <sys/bus.h> 89 hidbus_fill_rdesc_info(struct hid_rdesc_info *hri, const void *data, in hidbus_fill_rdesc_info() argument 94 hri->data = __DECONST(void *, data); in hidbus_fill_rdesc_info() 95 hri->len = len; in hidbus_fill_rdesc_info() 101 hri->isize = len == 0 ? HID_RSIZE_MAX : in hidbus_fill_rdesc_info() 102 hid_report_size_max(data, len, hid_input, &hri->iid); in hidbus_fill_rdesc_info() [all …]
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| /freebsd/sys/dev/acpica/ |
| H A D | acpi_pcib_acpi.c | 1 /*- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 #include <sys/bus.h> 66 int ap_bus; /* bios-assigned bus number */ 67 int ap_addr; /* device/func of PCI-Host bridge */ 73 static int acpi_pcib_acpi_probe(device_t bus); 74 static int acpi_pcib_acpi_attach(device_t bus); 79 static uint32_t acpi_pcib_read_config(device_t dev, u_int bus, 81 static void acpi_pcib_write_config(device_t dev, u_int bus, 82 u_int slot, u_int func, u_int reg, uint32_t data, [all …]
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | ecore_hsi_debug_tools.h | 2 * Copyright (c) 2017-2018 Cavium, Inc. 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 232 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */, 237 BIN_BUF_DBG_BUS_BLOCKS /* Debug Bus blocks */, 238 BIN_BUF_DBG_BUS_LINES /* Debug Bus lines */, 239 BIN_BUF_DBG_BUS_BLOCKS_USER_DATA /* Debug Bus blocks user data */, 240 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS /* Debug Bus line name offsets */, 250 u16 data; member 258 * Attention block per-type data 274 …struct dbg_attn_block_type_data per_type_data[2] /* attention block per-type data. Count must matc… [all …]
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| H A D | ecore_dbg_fw_funcs.c | 2 * Copyright (c) 2017-2018 Cavium, Inc. 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 168 return (r[0] < (r[1] - imm[0])); in cond8() 195 /******************************* Data Types **********************************/ 226 * Addresses are in bytes, sizes are in quad-regs. 282 /* Debug Bus Constraint operation constant definitions */ 344 /* Relative address of indirect TBUS data register (bits 0..7) */ 347 /* Relative address of indirect TBUS data register (bits 8..11) */ 363 …, val_width, amount) (((val) | ((val) << (val_width))) >> (amount)) & ((1 << (val_width)) - 1) 371 #define FIELD_BIT_MASK(type, field) (((1 << FIELD_BIT_SIZE(type, field)) - 1) << FIELD_DWORD_SHIF… [all …]
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| /freebsd/sys/dev/ppbus/ |
| H A D | ppb_1284.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * General purpose routines for the IEEE1284-1994 Standard 42 #include <sys/bus.h> 59 do_1284_wait(device_t bus, uint8_t mask, uint8_t status) in do_1284_wait() argument 61 return (ppb_poll_bus(bus, 4, mask, status, PPB_NOINTR | PPB_POLL)); in do_1284_wait() 65 do_peripheral_wait(device_t bus, uint8_t mask, uint8_t status) in do_peripheral_wait() argument 67 return (ppb_poll_bus(bus, 100, mask, status, PPB_NOINTR | PPB_POLL)); in do_peripheral_wait() 78 ppb_1284_reset_error(device_t bus, int state) in ppb_1284_reset_error() argument [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | video-interfaces.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sakari Ailus <sakari.ailus@linux.intel.com> 11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 14 Video data pipelines usually consist of external devices, e.g. camera sensors, 15 controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including 16 video DMA engines and video data processors. 20 bus controller nodes, e.g. I2C. [all …]
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| /freebsd/sys/dev/pci/controller/ |
| H A D | pci_n1sdp.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 9 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 #include <sys/bus.h> 68 "pci_n1sdp.c assumes a 4k or 16k page size when mapping the shared data"); 94 paddr = AP_NS_SHARED_MEM_BASE + sc->acpi.segment * BDF_TABLE_SIZE; in n1sdp_init() 112 paddr_rc = (vm_offset_t)shared_data->rc_base_addr; in n1sdp_init() 113 error = bus_space_map(sc->acpi.base.res->r_bustag, paddr_rc, in n1sdp_init() 114 PCI_CFG_SPACE_SIZE, 0, &sc->n1_bsh); in n1sdp_init() [all …]
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| /freebsd/sys/dev/iicbus/ |
| H A D | iiconf.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 #include <sys/bus.h> 44 * system errno value later. This lets controller- and bus-layer code get 54 * Translate IIC_Exxxxx status values to vaguely-equivelent errno values. 75 * IIC_ERRNO marker bit. If lots of high-order bits are set, in iic2errno() 76 * then it's one of the negative pseudo-errors such as ERESTART in iic2errno() 77 * and we return it as-is. Otherwise it's a plain "small in iic2errno() 94 iicbus_intr(device_t bus, int event, char *buf) in iicbus_intr() argument [all …]
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| /freebsd/usr.sbin/i2c/ |
| H A D | i2c.8 | 2 .\" Copyright (C) 2008-2009 Semihalf, Michal Hajduk and Bartlomiej Sieka 20 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 .Nd test I2C bus and slave devices 34 .Cm -a Ar address 44 .Cm -h 46 .Cm -i 49 .Op Ar - 51 .Cm -r 55 .Cm -s 62 utility can be used to perform raw data transfers (read or write) to devices [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | ov5640.txt | 1 * Omnivision OV5640 MIPI CSI-2 / parallel sensor 4 - compatible: should be "ovti,ov5640" 5 - clocks: reference to the xclk input clock. 6 - clock-names: should be "xclk". 7 - DOVDD-supply: Digital I/O voltage supply, 1.8 volts 8 - AVDD-supply: Analog voltage supply, 2.8 volts 9 - DVDD-supply: Digital core voltage supply, 1.5 volts 12 - reset-gpios: reference to the GPIO connected to the reset pin, if any. 14 - powerdown-gpios: reference to the GPIO connected to the powerdown pin, 16 - rotation: as defined in [all …]
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/ |
| H A D | recommended.json | 3 "PublicDescription": "Attributable Level 1 data cache access, read", 9 "PublicDescription": "Attributable Level 1 data cache access, write", 15 "PublicDescription": "Attributable Level 1 data cache refill, read", 21 "PublicDescription": "Attributable Level 1 data cache refill, write", 27 "PublicDescription": "Attributable Level 1 data cache refill, inner", 33 "PublicDescription": "Attributable Level 1 data cache refill, outer", 39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim", 42 "BriefDescription": "L1D cache Write-Back, victim" 45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency", 48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency" [all …]
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| H A D | armv8-recommended.json | 3 "PublicDescription": "Attributable Level 1 data cache access, read", 9 "PublicDescription": "Attributable Level 1 data cache access, write", 15 "PublicDescription": "Attributable Level 1 data cache refill, read", 21 "PublicDescription": "Attributable Level 1 data cache refill, write", 27 "PublicDescription": "Attributable Level 1 data cache refill, inner", 33 "PublicDescription": "Attributable Level 1 data cache refill, outer", 39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim", 42 "BriefDescription": "L1D cache Write-Back, victim" 45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency", 48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency" [all …]
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| /freebsd/lib/libpmc/ |
| H A D | pmc.atom.3 | 18 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual" 60 .%N "Order Number 253669-027US" 69 .Bl -column "PMC_CAP_INTERRUPT" "Support" 86 .Bl -tag -width indent 94 Configure the PMC to count the number of de-asserted to asserted 120 Events that require core-specificity to be specified use a 126 .Bl -tag -width indent [all …]
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| H A D | pmc.core2.3 | 18 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual" 60 .%N "Order Number 253669-027US" 67 Not all CPUs in this family implement fixed-function counters. 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 93 Configure the PMC to count the number of de-asserted to asserted 119 Events that require core-specificity to be specified use a [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/interconnect/ |
| H A D | samsung,exynos-bus.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung Exynos SoC Bus and Interconnect 10 - Chanwoo Choi <cw00.choi@samsung.com> 11 - Krzysztof Kozlowski <krzk@kernel.org> 14 The Samsung Exynos SoC has many buses for data transfer between DRAM and 15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses. 16 Generally, each bus of Exynos SoC includes a source clock and a power line, [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | mvebu-devbus.txt | 1 Device tree bindings for MVEBU Device Bus controllers 3 The Device Bus controller available in some Marvell's SoC allows to control 5 The actual devices are instantiated from the child nodes of a Device Bus node. 9 - compatible: Armada 370/XP SoC are supported using the 10 "marvell,mvebu-devbus" compatible string. 13 "marvell,orion-devbus" compatible string. 15 - reg: A resource specifier for the register space. 20 - #address-cells: Must be set to 1 21 - #size-cells: Must be set to 1 22 - ranges: Must be set up to reflect the memory layout with four [all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/bonnell/ |
| H A D | other.json | 3 "BriefDescription": "Bus queue is empty.", 11 "BriefDescription": "Number of Bus Not Ready signals asserted.", 19 "BriefDescription": "Number of Bus Not Ready signals asserted.", 27 "BriefDescription": "Bus cycles while processor receives data.", 35 "BriefDescription": "Bus cycles when data is sent on the bus.", 43 "BriefDescription": "Bus cycles when data is sent on the bus.", 83 "BriefDescription": "IO requests waiting in the bus queue.", 91 "BriefDescription": "Bus cycles when a LOCK signal is asserted.", 99 "BriefDescription": "Bus cycles when a LOCK signal is asserted.", 107 "BriefDescription": "Outstanding cacheable data read bus requests duration.", [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/devfreq/ |
| H A D | exynos-bus.txt | 1 * Generic Exynos Bus frequency device 3 The Samsung Exynos SoC has many buses for data transfer between DRAM 4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture 5 for buses. Generally, each bus of Exynos SoC includes a source clock 7 of the bus in runtime. To monitor the usage of each bus in runtime, 9 is able to measure the current load of sub-blocks. 11 The Exynos SoC includes the various sub-blocks which have the each AXI bus. 12 The each AXI bus has the owned source clock but, has not the only owned 13 power line. The power line might be shared among one more sub-blocks. 14 So, we can divide into two type of device as the role of each sub-block. [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | mipi-dsi-bus.txt | 4 The MIPI Display Serial Interface specifies a serial bus and a protocol for 6 define the syntax used to represent a DSI bus in a device tree. 8 This document describes DSI bus-specific properties only or defines existing 9 standard properties in the context of the DSI bus. 11 Each DSI host provides a DSI bus. The DSI host controller's node contains a 12 set of properties that characterize the bus. Child nodes describe individual 13 peripherals on that bus. 21 In addition to the standard properties and those defined by the parent bus of 25 - #address-cells: The number of cells required to represent an address on the 26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so [all …]
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