Lines Matching +full:data +full:- +full:bus

18 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
60 .%N "Order Number 253669-027US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
93 Configure the PMC to count the number of de-asserted to asserted
119 Events that require core-specificity to be specified use a
125 .Bl -tag -width indent
141 .Bl -tag -width indent
143 Measure events associated with this bus agent.
145 Measure events caused by any bus agent.
157 .Bl -tag -width "exclude"
175 .Bl -tag -width indent
197 .Bl -tag -width indent
213 .Bl -tag -width indent
223 .Bl -tag -width indent
323 transactions in the bus queue.
326 The number of Bus Not Ready signals asserted on the bus.
329 The number of bus cycles during which the processor is receiving data.
332 The number of bus cycles during which the Data Ready signal is asserted
333 on the bus.
336 The number of bus cycles during which the processor drives the
341 The number of bus cycles during which the processor drives the
346 The number of core cycles during which I/O requests wait in the bus
353 The number of bus cycles during which the
355 signal was asserted on the bus.
361 The number of pending full cache line read transactions on the bus
368 The number of partial bus transactions.
374 The number of instruction fetch full cache line bus transactions.
380 The number of invalidate bus transactions.
386 The number of partial write bus transactions.
392 The number of deferred bus transactions.
404 The number of memory bus transactions.
410 The number of bus transactions of any kind.
422 The number of completed I/O bus transactions due to
432 The number of Read For Ownership bus transactions.
438 The number explicit write-back bus transactions due to dirty line
445 The number of times the L1 data cache is snooped by the other core in
447 .It Li CPU_CLK_UNHALTED.BUS
450 The number of bus cycles when the core is not in the halt state.
459 The number of bus cycles during which the core remains unhalted and
477 The number of floating point operations that used data immediately
478 after the data was generated by a non floating point execution unit.
484 The number of times SIMD operations use data immediately after data,
485 was generated by a non-SIMD execution unit.
492 The number of Data TLB misses, including misses that result from
499 The number of Data TLB misses due to load operations.
502 The number of Data TLB misses due to store operations.
526 The number of snoop responses to bus transactions.
533 The number of floating point computational micro-ops executed.
597 The number of references to L1 data cache counting loads and stores of
601 The number of data reads and writes to cacheable memory.
611 The number of data reads from cacheable memory excluding locked
615 The number of data writes to cacheable memory excluding locked
619 The number of modified cache lines evicted from L1 data cache.
622 The number of modified lines allocated in L1 data cache.
625 The total number of outstanding L1 data cache misses at any clock.
628 The number of times L1 data cache requested to prefetch a data cache
632 The number of lines brought into L1 data cache.
647 The number of cycles that the L2 address bus is in use.
650 The number of cycles during which the L2 data bus is busy transferring
651 data to the core.
684 The number of locked accesses to cache lines that miss L1 data
729 The number of store operations that miss the L1 cache and request data
733 The number of loads blocked by the L1 data cache.
745 whose data value is not known.
778 The number of retired load operations that missed L1 data cache and
783 The number of retired load operations that missed L1 data cache.
805 The number of downward prefetches issued from the Data Prefetch Logic
809 The number of upward prefetches issued from the Data Prefetch Logic
860 The number of micro-ops dispatched for execution.
863 The number of cycles micro-ops were dispatched for execution on port
867 The number of cycles micro-ops were dispatched for execution on port
871 The number of cycles micro-ops were dispatched for execution on port
875 The number of cycles micro-ops were dispatched for execution on port
879 The number of cycles micro-ops were dispatched for execution on port
883 The number of cycles micro-ops were dispatched for execution on port
983 The number of SIMD saturated arithmetic micro-ops executed.
986 The number of SIMD micro-ops executed.
989 The number of SIMD packed arithmetic micro-ops executed.
992 The number of SIMD packed logical micro-ops executed.
995 The number of SIMD packed multiply micro-ops executed.
998 The number of SIMD pack micro-ops executed.
1001 The number of SIMD packed shift micro-ops executed.
1004 The number of SIMD unpack micro-ops executed.
1010 The number of times the bus stalled for snoops.
1028 The number of times SSE non-temporal store instructions were executed.
1057 The number of micro-ops retired that fused a load with another
1061 The number of store address calculations that fused into one micro-op.
1065 micro-op.
1068 The number of fused micro-ops retired.
1071 The number of non-fused micro-ops retired.
1074 The number of micro-ops retired.
1085 The following table shows the mapping between the PMC-independent
1089 .Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class"
1092 .It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP
1093 .It Li ic-misses Ta Li L1I_MISSES Ta Li PMC_CLASS_IAP
1096 .It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF