| /illumos-gate/usr/src/man/man8/ |
| H A D | trapstat.8 | 8 trapstat \- report trap statistics
12 \fB/usr/sbin/trapstat\fR [\fB-t\fR | \fB-T\fR | \fB-e\fR \fIentry\fR]
13 [\fB-C\fR \fIprocessor_set_id\fR | \fB-c\fR \fIcpulist\fR] [\fB-P\fR] [\fB-a\fR]
14 [\fB-r\fR \fIrate\fR] [ [\fIinterval\fR [\fIcount\fR]] | \fIcommand\fR | [\fIargs\fR]]
19 \fB/usr/sbin/trapstat\fR \fB-l\fR
24 The \fBtrapstat\fR utility gathers and displays run-time trap statistics on
25 UltraSPARC-based systems. The default output is a table of trap types and
33 specified with the \fB-c\fR or \fB-C\fR option.
36 Unless the \fB-r\fR option or the \fB-a\fR option is specified, the value
38 second. If the \fB-r\fR option is specified, the value corresponds to the
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| /illumos-gate/usr/src/uts/sun4u/os/ |
| H A D | cpr_impl.c | 146 * private struct for tlb handling
155 uint64_t skip; /* assumes TLB <= 64 locked entries */
161 * special handling for tlb info
192 * by client_handler() to jump into the prom. here we splice-in a wrapper
228 * Do not allow setting page size codes in MMU primary context in i_cpr_mp_setup()
264 for (cp = CPU->cpu_next; cp != CPU; cp = cp->cpu_next) { in i_cpr_mp_setup()
265 cp->cpu_flags = CPU_FROZEN; in i_cpr_mp_setup()
266 cp->cpu_m.mutex_ready = 0; in i_cpr_mp_setup()
269 for (cp = CPU->cpu_next; cp != CPU; cp = cp->cpu_next) in i_cpr_mp_setup()
270 restart_other_cpu(cp->cpu_id); in i_cpr_mp_setup()
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| H A D | ppage.c | 56 * The base is PPMAPBASE and its size is PPMAPSIZE. This memory is divided
88 * There are only 64 TLB entries on spitfire, 16 on cheetah
89 * (fully-associative TLB) so we allow the cpu module to tune the
140 * page. An avoid arg of -1 means you don't care, for instance pagezero.
166 if (color == -1) { in ppmapin()
167 if ((intptr_t)hint != -1L) { in ppmapin()
170 color = addr_to_vcolor(mmu_ptob(pp->p_pagenum)); in ppmapin()
241 nset = ((uintptr_t)va >> ppmap_shift) & (nsets - 1); in ppmapout()
260 * Find a slot in per CPU page copy area. Load up a locked TLB in the
262 * mapping is only temporary. If the thread migrates it'll get a TLB
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| /illumos-gate/usr/src/uts/sun4u/cpu/ |
| H A D | us3_cheetahplus_asm.S | 59 * By default we assume the Ecache is 2-way so we flush both
60 * ways. Even if the cache is direct-mapped no harm will come
64 * XXX - scr2 not used.
146 * We get here via trap 70 at TL>0->Software trap 0 at TL>0. We enter
158 * This macro turns off the D$/I$ if they are on and saves their
162 * point to the ch_err_tl1_data structure and the original D$/I$ state
197 * Flush the Ecache, using the largest possible cache size with the
198 * smallest possible line size since we can't get the actual sizes
222 * If we turned off the D$, then flush it and turn it back on.
230 * Flush the D$.
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| H A D | spitfire_asm.S | 66 * tmp3 = cache size \
67 * tmp1 = cache line size \
82 * tmp1 = cache line size \
93 bz,pn %icc, 5f /* branch if no valid sub-blocks */ ;\
109 * tmp1 = cache line size \
110 * tmp3 = cache size \
119 bz,pn %icc, 5f /* br if no valid sub-blocks */ ;\
144 * tmp2 = page size \
145 * tmp1 = cache line size \
160 #define DCACHE_FLUSHALL(size, linesize, tmp) \ argument
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| H A D | us3_cheetahplus.c | 62 #include <sys/fm/cpu/UltraSPARC-III.h>
133 vac_mask = MMU_PAGEMASK & (vac_size - 1); in cpu_fiximp()
143 * Use Panther values for Panther-only domains.
158 /* fix hwcaps for USIV+-only domains */ in cpu_fix_allpanther()
236 endtick += (tick - lasttick); in send_mondo_set()
242 cpuid = -1; in send_mondo_set()
250 if (cheetah_sendmondo_recover && cpuid != -1 && in send_mondo_set()
270 "[%d NACK %d BUSY]\nIDSR 0x%" in send_mondo_set()
301 lo = lowbit(cpus_left) - 1; in send_mondo_set()
315 for ((index = ((int)next - 1)); in send_mondo_set()
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| H A D | us3_common_mmu.c | 45 * pan_disable_ism_large_pages and pan_disable_large_pages are the Panther-
48 * for Panther-only systems.
50 * chpjag_disable_large_pages is the Ch/Jaguar-specific version of
67 * The function returns the USIII+(i)-IV+ mmu-specific values for the
70 * already contain the generic sparc 4 page size info, and the return
71 * values are or'd with those values.
116 * P_pgsz0 and sfmmu_pgsz[1] is used in P_pgsz1, as per Figure F-1-1
118 * Supplement and Table 15-21 DMMU Primary Context Register in the
136 * for Panther-only systems. It may be called from set_platform_defaults,
137 * if some value other than 4M is desired, for Panther-only systems.
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| H A D | opl_olympus.c | 27 * Support for Olympus-C (SPARC64-VI) and Jupiter (SPARC64-VII).
65 #include <sys/fm/cpu/SPARC64-VI.h>
100 * Set to 1 if booted with all Jupiter cpus (all-Jupiter features enabled).
151 "TLB MultiHit", FM_EREPORT_PAYLOAD_SYNC,
154 "TLB Parity", FM_EREPORT_PAYLOAD_SYNC,
264 "l1-dcache-size", &dcache_size, OPL_DCACHE_SIZE, in cpu_fiximp()
265 "l1-dcache-line-size", &dcache_linesize, OPL_DCACHE_LSIZE, in cpu_fiximp()
266 "l1-icache-size", &icache_size, OPL_ICACHE_SIZE, in cpu_fiximp()
267 "l1-icache-line-size", &icache_linesize, OPL_ICACHE_LSIZE, in cpu_fiximp()
268 "l2-cache-size", &ecache_size, OPL_ECACHE_SIZE, in cpu_fiximp()
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| H A D | us3_common_asm.S | 72 * tmp3 = cache size \
73 * tmp1 = cache line size \
88 * tmp1 = cache line size \
108 * tmp1 = cache line size \
109 * tmp3 = cache size \
118 bz,pn %icc, 5f /* br if no valid sub-blocks */ ;\
133 * dcache size = 64K, one way 16K
148 * tmp1 = cache line size \
156 * tmp2 = page size \
176 * flush page from the tlb
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| /illumos-gate/usr/src/uts/sun4/io/ |
| H A D | trapstat.c | 54 * -------------------------------------------------------------------
60 * of machine-specific traps. The lack of insight has been especially acute
61 * on UltraSPARC microprocessors: because these microprocessors handle TLB
64 * increasingly outstripped TLB reach, this has become increasingly true.
73 * entry increments a per-trap, in-memory counter and then jumps to the actual,
76 * (Note that per-CPU statistics fall out by creating a different trap table
81 * While the idea is straight-forward, a nuance of SPARC V9 slightly
94 * +--------------------------------+- 3ff
98 * |- - - - - - - - - - - - - - - - +- 300
99 * |- - - - - - - - - - - - - - - - +- 2ff
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| /illumos-gate/usr/src/psm/stand/boot/sparc/sun4/sys/ |
| H A D | prom_plat.h | 40 * This file contains external platform-specific promif interface definitions.
43 * Common sun4 subset for the IEEE 1275-1994 compliant prom.
49 * Routines with fine-grained memory and MMU control are platform-dependent.
59 * R (read - soft) Set (Prom is not required to implement soft bits)
60 * X (exec - soft) Set (Prom is not required to implement soft bits)
65 * The following fields are initialized as follows in the TTE-data for any
74 * Page size of Prom mappings are typically 8k, "modify" cannot change
77 * If the virtualized "mode" is -1, the defaults as shown above are used,
80 * property contains the actual tte-data, not the virtualized "mode".
84 * and remove locked mappings. (SUNW,{i,d}tlb-load).
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| /illumos-gate/usr/src/uts/sun4v/sys/ |
| H A D | prom_plat.h | 43 * This file contains external platform-specific promif interface definitions.
46 * This version of the file is for the IEEE 1275-1994 compliant sun4u prom.
52 * Routines with fine-grained memory and MMU control are platform-dependent.
62 * R (read - soft) Set (Prom is not required to implement soft bits)
63 * X (exec - soft) Set (Prom is not required to implement soft bits)
68 * The following fields are initialized as follows in the TTE-data for any
77 * Page size of Prom mappings are typically 8k, "modify" cannot change
80 * If the virtualized "mode" is -1, the defaults as shown above are used,
83 * property contains the actual tte-data, not the virtualized "mode".
87 * and remove locked mappings. (SUNW,{i,d}tlb-load).
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| /illumos-gate/usr/src/uts/sun4u/sys/ |
| H A D | prom_plat.h | 44 * This file contains external platform-specific promif interface definitions.
47 * This version of the file is for the IEEE 1275-1994 compliant sun4u prom.
53 * Routines with fine-grained memory and MMU control are platform-dependent.
63 * R (read - soft) Set (Prom is not required to implement soft bits)
64 * X (exec - soft) Set (Prom is not required to implement soft bits)
69 * The following fields are initialized as follows in the TTE-data for any
78 * Page size of Prom mappings are typically 8k, "modify" cannot change
81 * If the virtualized "mode" is -1, the defaults as shown above are used,
84 * property contains the actual tte-data, not the virtualized "mode".
88 * and remove locked mappings. (SUNW,{i,d}tlb-load).
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| H A D | mmu.h | 58 #define MMU_TAG_ACCESS 0x30 /* tlb tag access */
61 #define MMU_TSB_PX 0x48 /* i/d tsb primary extension reg */
62 #define MMU_TSB_SX 0x50 /* d tsb secondary extension reg */
63 #define MMU_TSB_NX 0x58 /* i/d tsb nucleus extension reg */
64 #define MMU_TAG_ACCESS_EXT 0x60 /* tlb tag access extension reg */
65 #define MMU_SHARED_CONTEXT 0x68 /* SPARC64-VII shared context */
75 * |--------------|------|----------|----|---|------|------|---|----|---|
84 #define SFSR_E 0x00000040 /* side-effect */
115 * +-----+---------+------+-------------------------+
116 * | 000 | context | -- | virtual address [63:22] |
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| /illumos-gate/usr/src/psm/stand/cpr/sparcv9/sun4u/ |
| H A D | cprboot.c | 27 * cprboot - prom client that restores kadb/kernel pages
30 * reset boot-file/boot-device to their original values
133 * will be found without any special-case code in get_bootargs()
140 if (cp - argp) { in get_bootargs()
142 if ((argv - cb_args) == (CB_MAXARGS - 1)) in get_bootargs()
151 prom_printf(" %d: \"%s\"\n", in get_bootargs()
152 (int)(argv - cb_args), *argv); in get_bootargs()
164 "Usage: boot -F %s [-R] [-S <diskpath>]\n%s\n\n", in usage()
171 * bootargs should start with "-F cprboot"
186 /* expect "-F" */ in check_bootargs()
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| H A D | machdep.c | 86 mdlen = cmach.md_size - sizeof (csu_md_t); in cb_check_machdep()
122 * a sequence of null-terminated strings stored contiguously. in cb_interpret()
135 s = sizeof (minibuf) - 4; in cb_interpret()
143 bytes -= wlen; in cb_interpret()
166 tname = 'd'; in restore_tlb()
173 if (utp->va_tag == 0) in restore_tlb()
175 virt = (caddr_t)utp->va_tag; in restore_tlb()
176 (*tfunc)(utp->index, virt, &utp->tte); in restore_tlb()
178 prom_printf(" cpu_id %d: write %ctlb " in restore_tlb()
179 "(index %x, virt 0x%lx, size 0x%x)\n", in restore_tlb()
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| H A D | pages.c | 49 * page had already been moved - and would confuse the compare in shuffle_pages()
53 tail_ppn = descp->cpd_pfn + descp->cpd_pages; in shuffle_pages()
54 for (dst_ppn = descp->cpd_pfn; dst_ppn < tail_ppn; dst_ppn++) { in shuffle_pages()
84 dst_off = mmu_ptob(dst_ppn - sfile.low_ppn); in shuffle_pages()
92 * map-in source statefile buffer pages (read-only) at CB_SRC_VIRT;
103 dtlb_index = cb_dents - CB_MAX_KPAGES - 1; in mapin_buf_pages()
113 dtlb_index--; in mapin_buf_pages()
120 * map-in destination kernel pages (read/write) at CB_DST_VIRT
129 dtlb_index = cb_dents - 1; in mapin_dst_pages()
131 dst_ppn = descp->cpd_pfn; in mapin_dst_pages()
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| /illumos-gate/usr/src/uts/sun4v/os/ |
| H A D | fillsysinfo.c | 95 uint_t vac_mask = MMU_PAGEMASK & (S_VAC_SIZE - 1);
113 uint64_t associativity = 0, linesize = 0, size = 0; in fill_cpu() local
119 /* All out-of-range cpus will be stopped later. */ in fill_cpu()
121 cmn_err(CE_CONT, "fill_cpu: out of range cpuid %ld - " in fill_cpu()
128 cpunode->cpuid = (int)cpuid; in fill_cpu()
129 cpunode->device_id = cpuid; in fill_cpu()
131 if (sizeof (cpunode->fru_fmri) > strlen(CPU_FRU_FMRI)) in fill_cpu()
132 (void) strcpy(cpunode->fru_fmri, CPU_FRU_FMRI); in fill_cpu()
142 if (strlen(namebufp) > sizeof (cpunode->name)) in fill_cpu()
145 (void) strcpy(cpunode->name, namebufp); in fill_cpu()
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| /illumos-gate/usr/src/uts/sun4u/io/ |
| H A D | iommu.c | 26 * Copyright 2012 Garrett D'Amore <garrett@damore.org>. All rights reserved.
99 * the TLB flush code to use diagnostic registers. This value was determined
138 softsp->iommu_ctrl_reg = REG_ADDR(address, OFF_IOMMU_CTRL_REG); in iommu_init()
139 softsp->tsb_base_addr = REG_ADDR(address, OFF_TSB_BASE_ADDR); in iommu_init()
140 softsp->iommu_flush_reg = REG_ADDR(address, OFF_IOMMU_FLUSH_REG); in iommu_init()
141 softsp->iommu_tlb_tag = REG_ADDR(address, OFF_IOMMU_TLB_TAG); in iommu_init()
142 softsp->iommu_tlb_data = REG_ADDR(address, OFF_IOMMU_TLB_DATA); in iommu_init()
146 mutex_init(&softsp->dma_pool_lock, NULL, MUTEX_DEFAULT, NULL); in iommu_init()
147 mutex_init(&softsp->intr_poll_list_lock, NULL, MUTEX_DEFAULT, NULL); in iommu_init()
150 if ((softsp->iommu_tsb_cookie = iommu_tsb_alloc(softsp->upa_id)) == in iommu_init()
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| /illumos-gate/usr/src/uts/common/xen/public/ |
| H A D | xen.h | 30 #include "xen-compat.h"
45 #include "arch-x86/xen.h"
47 #include "arch-ia64.h"
107 /* Architecture-specific hypercall definitions. */
127 /* New event-channel and physdev hypercalls introduced in 0x00030202. */
145 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
146 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
148 * allocated to VCPU0 but can subsequently be re-bound.
159 /* Architecture-specific VIRQ definitions. */
172 * MMU-UPDATE REQUESTS
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| /illumos-gate/usr/src/uts/sfmmu/vm/ |
| H A D | hat_sfmmu.c | 31 * VM - Hardware Address Translation management for Spitfire MMU.
97 ASSERT(SF_RGNMAP_TEST(hat->sfmmu_hmeregion_map, rid)); \
99 _srdp = (hat)->sfmmu_srdp; \
101 ASSERT(_srdp->srd_refcnt != 0); \
102 _rgnp = _srdp->srd_hmergnp[(rid)]; \
103 ASSERT(_rgnp != NULL && _rgnp->rgn_id == rid); \
104 ASSERT(_rgnp->rgn_refcnt != 0); \
105 ASSERT(!(_rgnp->rgn_flags & SFMMU_REGION_FREE)); \
106 ASSERT((_rgnp->rgn_flags & SFMMU_REGION_TYPE_MASK) == \
108 ASSERT((saddr) >= _rgnp->rgn_saddr); \
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| /illumos-gate/usr/src/uts/i86pc/vm/ |
| H A D | htable.c | 101 #define HTABLE_MUTEX_HASH(h) ((h) & (NUM_HTABLE_MUTEX - 1))
118 * A counter to track if we are stealing or reaping htables. When non-zero
204 * PT_WRITABLE | PT_VALID - regular kpm mapping
205 * PT_VALID - make mapping read-only
206 * 0 - remove mapping
208 * returns 0 on success. non-zero for failure.
305 pfn = pp->p_pagenum; in ptable_alloc()
331 ASSERT(pfn == pp->p_pagenum); in ptable_free()
338 u_offset_t off = pp->p_offset; in ptable_free()
359 ht->ht_hat = NULL; /* no longer tied to a hat */ in htable_put_reserve()
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| /illumos-gate/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_iommu.c | 26 * Copyright 2012 Garrett D'Amore <garrett@damore.org>. All rights reserved.
52 dev_info_t *dip = pci_p->pci_dip; in iommu_create()
68 pci_p->pci_iommu_p = iommu_p; in iommu_create()
69 iommu_p->iommu_pci_p = pci_p; in iommu_create()
70 iommu_p->iommu_inst = ddi_get_instance(dip); in iommu_create()
75 iommu_p->iommu_dvma_end = pci_iommu_dvma_end; in iommu_create()
81 iommu_p->iommu_ctrl_reg = in iommu_create()
83 iommu_p->iommu_tsb_base_addr_reg = in iommu_create()
85 iommu_p->iommu_flush_page_reg = in iommu_create()
92 iommu_p->iommu_tsb_vaddr = /* retrieve TSB VA reserved by system */ in iommu_create()
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| /illumos-gate/usr/src/uts/intel/os/ |
| H A D | cpuid.c | 54 * multi-processing (SMT), etc.
56 * ------------------------
58 * ------------------------
80 * AMD adds non-Intel compatible
104 * various extensions. For example, AMD-
122 * Some leaves are broken down into sub-leaves. This means that the value
124 * example, Intel uses the value in %ecx on leaf 7 to indicate a sub-leaf to get
130 * program is in 64-bit mode. When executing in 64-bit mode, the upper
134 * ----------------------
136 * ----------------------
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| /illumos-gate/usr/src/uts/sun4u/vm/ |
| H A D | mach_sfmmu.h | 27 * VM - Hardware Address Translation management.
55 * Platforms that use UTSB_PHYS do not allocate 2 locked TLB entries to access
61 #define SCRATCHPAD_UTSBREG2 OPL_SCRATCHPAD_UTSBREG4 /* 4M-256M pages */
62 #define SCRATCHPAD_UTSBREG3 OPL_SCRATCHPAD_UTSBREG5 /* 8K-512K pages */
63 #define SCRATCHPAD_UTSBREG4 OPL_SCRATCHPAD_UTSBREG6 /* 4M-256M pages */
285 bnz,pt %xcc, label##4; /* if ref bit set-skip ahead */ \
289 blt %icc, label##2; /* skip flush if FJ-OPL cpus */ \
342 blt %icc, label##2; /* skip flush if FJ-OPL cpus */ \
377 * can vary depending upon the TSB slab size being used on the
438 * Load the locked TSB TLB entry.
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