xref: /linux/tools/perf/Documentation/perf-mem.txt (revision 36ec807b627b4c0a0a382f0ae48eac7187d14b2b)
1028f12eeSStephane Eranianperf-mem(1)
2028f12eeSStephane Eranian===========
3028f12eeSStephane Eranian
4028f12eeSStephane EranianNAME
5028f12eeSStephane Eranian----
6028f12eeSStephane Eranianperf-mem - Profile memory accesses
7028f12eeSStephane Eranian
8028f12eeSStephane EranianSYNOPSIS
9028f12eeSStephane Eranian--------
10028f12eeSStephane Eranian[verse]
11028f12eeSStephane Eranian'perf mem' [<options>] (record [<command>] | report)
12028f12eeSStephane Eranian
13028f12eeSStephane EranianDESCRIPTION
14028f12eeSStephane Eranian-----------
1567121f85SStephane Eranian"perf mem record" runs a command and gathers memory operation data
16028f12eeSStephane Eranianfrom it, into perf.data. Perf record options are accepted and are passed through.
17028f12eeSStephane Eranian
1867121f85SStephane Eranian"perf mem report" displays the result. It invokes perf report with the
1967121f85SStephane Eranianright set of options to display a memory access profile. By default, loads
2067121f85SStephane Eranianand stores are sampled. Use the -t option to limit to loads or stores.
21028f12eeSStephane Eranian
22b6394097SAndi KleenNote that on Intel systems the memory latency reported is the use-latency,
23b6394097SAndi Kleennot the pure load (or store latency). Use latency includes any pipeline
24*a93c83ecSIan Rogersqueuing delays in addition to the memory subsystem latency.
25b6394097SAndi Kleen
2686569c0aSJames ClarkOn Arm64 this uses SPE to sample load and store operations, therefore hardware
2786569c0aSJames Clarkand kernel support is required. See linkperf:perf-arm-spe[1] for a setup guide.
2886569c0aSJames ClarkDue to the statistical nature of SPE sampling, not every memory operation will
2986569c0aSJames Clarkbe sampled.
3086569c0aSJames Clark
31028f12eeSStephane EranianOPTIONS
32028f12eeSStephane Eranian-------
33028f12eeSStephane Eranian<command>...::
34028f12eeSStephane Eranian	Any command you can specify in a shell.
35028f12eeSStephane Eranian
363138a2efSSangwon Hong-i::
373138a2efSSangwon Hong--input=<file>::
383138a2efSSangwon Hong	Input file name.
393138a2efSSangwon Hong
407e99b197SSangwon Hong-f::
417e99b197SSangwon Hong--force::
427e99b197SSangwon Hong	Don't do ownership validation
437e99b197SSangwon Hong
44028f12eeSStephane Eranian-t::
453138a2efSSangwon Hong--type=<type>::
4667121f85SStephane Eranian	Select the memory operation type: load or store (default: load,store)
47028f12eeSStephane Eranian
48028f12eeSStephane Eranian-D::
493138a2efSSangwon Hong--dump-raw-samples::
50028f12eeSStephane Eranian	Dump the raw decoded samples on the screen in a format that is easy to parse with
51028f12eeSStephane Eranian	one sample per line.
52028f12eeSStephane Eranian
53028f12eeSStephane Eranian-x::
543138a2efSSangwon Hong--field-separator=<separator>::
55028f12eeSStephane Eranian	Specify the field separator used when dump raw samples (-D option). By default,
56028f12eeSStephane Eranian	The separator is the space character.
57028f12eeSStephane Eranian
58028f12eeSStephane Eranian-C::
593138a2efSSangwon Hong--cpu=<cpu>::
603138a2efSSangwon Hong	Monitor only on the list of CPUs provided. Multiple CPUs can be provided as a
613138a2efSSangwon Hong        comma-separated list with no space: 0,1. Ranges of CPUs are specified with -: 0-2. Default
623138a2efSSangwon Hong        is to monitor all CPUS.
633138a2efSSangwon Hong-U::
643138a2efSSangwon Hong--hide-unresolved::
653138a2efSSangwon Hong	Only display entries resolved to a symbol.
663138a2efSSangwon Hong
673138a2efSSangwon Hong-p::
683138a2efSSangwon Hong--phys-data::
693138a2efSSangwon Hong	Record/Report sample physical addresses
703138a2efSSangwon Hong
7106280e3bSKan Liang--data-page-size::
7206280e3bSKan Liang	Record/Report sample data address page size
7306280e3bSKan Liang
743138a2efSSangwon HongRECORD OPTIONS
753138a2efSSangwon Hong--------------
763138a2efSSangwon Hong-e::
773138a2efSSangwon Hong--event <event>::
783138a2efSSangwon Hong	Event selector. Use 'perf mem record -e list' to list available events.
79028f12eeSStephane Eranian
80ad16511bSJiri Olsa-K::
81ad16511bSJiri Olsa--all-kernel::
82ad16511bSJiri Olsa	Configure all used events to run in kernel space.
83ad16511bSJiri Olsa
84ad16511bSJiri Olsa-U::
85ad16511bSJiri Olsa--all-user::
86ad16511bSJiri Olsa	Configure all used events to run in user space.
87ad16511bSJiri Olsa
883138a2efSSangwon Hong-v::
893138a2efSSangwon Hong--verbose::
903138a2efSSangwon Hong	Be more verbose (show counter open errors, etc)
91b0d745b3SJiri Olsa
923138a2efSSangwon Hong--ldlat <n>::
93f7b58cbdSRavi Bangoria	Specify desired latency for loads event. Supported on Intel and Arm64
94f7b58cbdSRavi Bangoria	processors only. Ignored on other archs.
95c35aeb9dSKan Liang
96a7e9eab3SAndi KleenIn addition, for report all perf report options are valid, and for record
97a7e9eab3SAndi Kleenall perf record options.
98a7e9eab3SAndi Kleen
99028f12eeSStephane EranianSEE ALSO
100028f12eeSStephane Eranian--------
10186569c0aSJames Clarklinkperf:perf-record[1], linkperf:perf-report[1], linkperf:perf-arm-spe[1]
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