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/linux/arch/arm64/boot/dts/amd/
H A Delba-16core.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu-map {
44 compatible = "arm,cortex-a72";
46 next-level-cache = <&l2_0>;
47 enable-method = "psci";
52 compatible = "arm,cortex-a72";
54 next-level-cache = <&l2_0>;
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0-octa-core.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap810-ap0.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 compatible = "marvell,armada-ap810-octa";
18 compatible = "arm,cortex-a72";
20 enable-method = "psci";
24 compatible = "arm,cortex-a72";
26 enable-method = "psci";
30 compatible = "arm,cortex-a72";
[all …]
H A Darmada-ap806-quad.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
[all …]
H A Darmada-ap807-quad.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap807.dtsi"
12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
[all …]
H A Darmada-ap806-dual.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
[all …]
/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72-pmu";
25 compatible = "arm,cortex-a72";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
35 compatible = "arm,cortex-a72";
[all …]
H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
11 #include "k3-j784s4-j742s2-common.dtsi"
18 #address-cells = <1>;
19 #size-cells = <0>;
20 cpu-map {
59 compatible = "arm,cortex-a72";
62 enable-method = "psci";
63 i-cache-size = <0xc000>;
64 i-cache-line-size = <64>;
[all …]
H A Dk3-j721s2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/ti,sci_pm_domain.h>
15 #include "k3-pinctrl.h"
21 interrupt-parent = <&gic500>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 #address-cells = <1>;
[all …]
H A Dk3-j7200.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/soc/ti,sci_pm_domain.h>
12 #include "k3-pinctrl.h"
17 interrupt-parent = <&gic500>;
18 #address-cells = <2>;
19 #size-cells = <2>;
24 #address-cells = <1>;
[all …]
H A Dk3-j721e.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/soc/ti,sci_pm_domain.h>
12 #include "k3-pinctrl.h"
17 interrupt-parent = <&gic500>;
18 #address-cells = <2>;
19 #size-cells = <2>;
24 #address-cells = <1>;
[all …]
/linux/tools/perf/pmu-events/arch/arm64/
H A Dmapfile.csv10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd020,v1,arm/cortex-a34,core
16 0x00000000410fd030,v1,arm/cortex-a53,core
17 0x00000000420f1000,v1,arm/cortex-a53,core
18 0x00000000410fd040,v1,arm/cortex-a35,core
19 0x00000000410fd050,v1,arm/cortex-a55,core
20 0x00000000410fd060,v1,arm/cortex-a65-e1,core
21 0x00000000410fd4a0,v1,arm/cortex-a65-e1,core
22 0x00000000410fd070,v1,arm/cortex-a57-a72,core
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-r2.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
[all …]
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
[all …]
/linux/arch/arm64/boot/dts/tesla/
H A Dfsd.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dthermal-idle.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
27 '#cooling-cells':
31 the cooling-maps reference. The first cell is the minimum cooling state
34 duration-us:
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
[all …]
/linux/Documentation/arch/arm/
H A Dmarvell.rst13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
[all …]
/linux/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
275 ARM 64-bit (AArch64) Linux support.
283 # required due to use of the -Zfixed-x18 flag.
286 # -Zsanitizer=shadow-call-stack flag.
296 depends on $(cc-option,-fpatchable-function-entry=2)
322 # VA_BITS - PAGE_SHIFT - 3
400 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
405 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
455 at stage-2.
463 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
[all …]
/linux/drivers/soc/bcm/brcmstb/
H A Dbiuctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
26 /* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
63 if (offset == -1 || in cbc_readl()
65 return (u32)-1; in cbc_readl()
74 if (offset == -1 || in cbc_writel()
83 [CPU_MCP_FLOW_REG] = -1,
84 [CPU_WRITEBACK_CTRL_REG] = -1,
85 [RAC_CONFIG0_REG] = -1,
86 [RAC_CONFIG1_REG] = -1,
93 [CPU_WRITEBACK_CTRL_REG] = -1,
[all …]

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