Lines Matching +full:cortex +full:- +full:a72
1 # SPDX-License-Identifier: GPL-2.0-only
275 ARM 64-bit (AArch64) Linux support.
283 # required due to use of the -Zfixed-x18 flag.
286 # -Zsanitizer=shadow-call-stack flag.
296 depends on $(cc-option,-fpatchable-function-entry=2)
322 # VA_BITS - PAGE_SHIFT - 3
400 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
405 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
455 at stage-2.
463 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
468 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
471 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
477 data cache clean-and-invalidate.
485 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
490 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
499 data cache clean-and-invalidate.
507 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
512 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
515 If a Cortex-A53 processor is executing a store or prefetch for
522 data cache clean-and-invalidate.
530 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
535 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
544 data cache clean-and-invalidate.
552 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
556 erratum 832075 on Cortex-A57 parts up to r1p2.
558 Affected Cortex-A57 parts might deadlock when exclusive load/store
559 instructions to Write-Back memory are mixed with Device loads.
561 The workaround is to promote device loads to use Load-Acquire
570 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
574 erratum 834220 on Cortex-A57 parts up to r1p2.
576 Affected Cortex-A57 parts might report a Stage 2 translation
590 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
594 This option removes the AES hwcap for aarch32 user-space to
595 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
606 bool "Cortex-A53: 845719: a load might read incorrect data"
611 erratum 845719 on Cortex-A53 parts up to r0p4.
613 When running a compat (AArch32) userspace on an affected Cortex-A53
619 return to a 32-bit task.
627 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
630 This option links the kernel with '--fix-cortex-a53-843419' and
633 Cortex-A53 parts up to r0p4.
638 def_bool $(ld-option,--fix-cortex-a53-843419)
641 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
644 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
646 Affected Cortex-A55 cores (all revisions) could cause incorrect
648 without a break-before-make. The workaround is to disable the usage
655 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
659 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
662 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
672 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
676 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
678 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
685 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
689 This option adds work arounds for ARM Cortex-A57 erratum 1319537
690 and A72 erratum 1319367
692 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
698 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
702 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
704 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
714 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
717 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
719 Under very rare circumstances, affected Cortex-A55 CPUs
720 may not handle a race between a break-before-make sequence on one
730 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
733 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
735 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
739 break-before-make sequence, then under very rare circumstances
747 bool "Cortex-A76: Software Step might prevent interrupt recognition"
750 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
752 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
765 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
767 This option adds a workaround for ARM Neoverse-N1 erratum
770 Affected Neoverse-N1 cores could execute a stale instruction when
775 forces user-space to perform cache maintenance.
780 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
783 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
785 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
786 of a store-exclusive or read of PAR_EL1 and a load with device or
787 non-cacheable memory attributes. The workaround depends on a firmware
803 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
806 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
807 Affected Cortex-A510 might not respect the ordering rules for
814 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
817 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
818 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
826 previous guest entry, and can be restored from the in-memory copy.
831 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
834 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
835 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
839 user-space should not be using these instructions.
844 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
849 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
851 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
862 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
867 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
869 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
883 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
887 Enable workaround for ARM Cortex-A710 erratum 2054223
898 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
902 Enable workaround for ARM Neoverse-N2 erratum 2067961
916 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
921 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
923 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
934 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
939 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
941 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
952 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
955 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
957 Under very rare circumstances, affected Cortex-A510 CPUs
958 may not handle a race between a break-before-make sequence on one
968 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
972 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
974 Affected Cortex-A510 core might fail to write into system registers after the
986 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
990 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
992 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1009 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1013 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1015 Affected Cortex-A510 core might cause trace data corruption, when being written
1027 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1031 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1034 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1044 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1047 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1049 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1050 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1053 Only user-space does executable to non-executable permission transition via
1054 mprotect() system call. Workaround the problem by doing a break-before-make
1063 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1067 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1069 On an affected Cortex-A520 core, a speculatively executed unprivileged
1077 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1081 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1083 On an affected Cortex-A510 core, a speculatively executed unprivileged
1091 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1096 * ARM Cortex-A76 erratum 3324349
1097 * ARM Cortex-A77 erratum 3324348
1098 * ARM Cortex-A78 erratum 3324344
1099 * ARM Cortex-A78C erratum 3324346
1100 * ARM Cortex-A78C erratum 3324347
1101 * ARM Cortex-A710 erratam 3324338
1102 * ARM Cortex-A715 errartum 3456084
1103 * ARM Cortex-A720 erratum 3456091
1104 * ARM Cortex-A725 erratum 3456106
1105 * ARM Cortex-X1 erratum 3324344
1106 * ARM Cortex-X1C erratum 3324346
1107 * ARM Cortex-X2 erratum 3324338
1108 * ARM Cortex-X3 erratum 3324335
1109 * ARM Cortex-X4 erratum 3194386
1110 * ARM Cortex-X925 erratum 3324334
1111 * ARM Neoverse-N1 erratum 3324349
1113 * ARM Neoverse-N3 erratum 3456111
1114 * ARM Neoverse-V1 erratum 3324341
1116 * ARM Neoverse-V3 erratum 3312417
1124 SSBS. The presence of the SSBS special-purpose register is hidden
1136 This implements two gicv3-its errata workarounds for ThunderX. Both
1176 contains data for a non-current ASID. The fix is to
1187 interrupts in host. Trapping both GICv3 group-0 and group-1
1210 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1213 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1214 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1218 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1219 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1220 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1221 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1224 The workaround only affects the Fujitsu-A64FX.
1295 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1305 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1312 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1316 MSI doorbell writes with non-zero values for the device ID.
1348 look-up. AArch32 emulation requires applications compiled
1362 bool "36-bit" if EXPERT
1366 bool "39-bit"
1370 bool "42-bit"
1374 bool "47-bit"
1378 bool "48-bit"
1381 bool "52-bit"
1384 Enable 52-bit virtual addressing for userspace when explicitly
1385 requested via a hint to mmap(). The kernel will also use 52-bit
1387 this feature is available, otherwise it reverts to 48-bit).
1389 NOTE: Enabling 52-bit virtual addressing in conjunction with
1392 impact on its susceptibility to brute-force attacks.
1394 If unsure, select 48-bit virtual addressing instead.
1399 bool "Force 52-bit virtual addresses for userspace"
1402 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1403 to maintain compatibility with older software by providing 48-bit VAs
1406 This configuration option disables the 48-bit compatibility logic, and
1407 forces all userspace addresses to be 52-bit on HW that supports it. One
1428 bool "48-bit"
1432 bool "52-bit"
1436 Enable support for a 52-bit physical address space, introduced as
1437 part of the ARMv8.2-LPA extension.
1440 do not support ARMv8.2-LPA, but with some added memory overhead (and
1463 bool "Build big-endian kernel"
1464 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1467 Say Y if you plan on running a kernel with a big-endian userspace.
1470 bool "Build little-endian kernel"
1472 Say Y if you plan on running a kernel with a little-endian userspace.
1478 bool "Multi-core scheduler support"
1480 Multi-core scheduler support improves the CPU scheduler's decision
1481 making when dealing with multi-core CPU chips at a cost of slightly
1490 by sharing mid-level caches, last-level cache tags or internal
1501 int "Maximum number of CPUs (2-4096)"
1506 bool "Support for hot-pluggable CPUs"
1522 Enable NUMA (Non-Uniform Memory Access) support.
1550 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1619 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1622 # ----+-------------------+--------------+----------------------+-------------------------+
1650 Speculation attacks against some high-performance processors can
1662 Speculation attacks against some high-performance processors can
1664 When taking an exception from user-space, a sequence of branches
1671 Apply read-only attributes of VM areas to the linear alias of
1672 the backing pages as well. This prevents code or read-only data
1686 user-space memory directly by pointing TTBR0_EL1 to a reserved
1697 Documentation/arch/arm64/tagged-address-abi.rst.
1700 bool "Kernel support for 32-bit EL0"
1706 This option enables support for a 32-bit EL0 running under a 64-bit
1707 kernel at EL1. AArch32-specific components such as system calls,
1715 If you want to execute 32-bit userspace applications, say Y.
1720 bool "Enable kuser helpers page for 32-bit applications"
1723 Warning: disabling this option may break 32-bit user programs.
1747 bool "Enable vDSO for 32-bit applications"
1753 Place in the process address space of 32-bit applications an
1757 You must have a 32-bit build of glibc 2.22 or later for programs
1761 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1765 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1766 otherwise with '-marm'.
1769 bool "Fix up misaligned multi-word loads and stores in user space"
1811 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1812 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1827 The SETEND instruction alters the data-endianness of the
1835 for this feature to be enabled. If a new CPU - which doesn't support mixed
1836 endian - is hotplugged in after this feature has been enabled, there could
1855 Similarly, writes to read-only pages with the DBM bit set will
1856 clear the read-only bit (AP[2]) instead of raising a
1860 to work on pre-ARMv8.1 hardware and the performance impact is
1868 prevents the kernel or hypervisor from accessing user-space (EL0)
1878 def_bool $(as-instr,.arch_extension lse)
1893 Say Y here to make use of these instructions for the in-kernel
1904 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1907 def_bool $(as-instr,.arch armv8.2-a+sha3)
1967 context-switched along with the process.
1990 If the compiler supports the -mbranch-protection or
1991 -msign-return-address flag (e.g. GCC 7 or later), then this option
2002 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
2006 def_bool $(cc-option,-msign-return-address=all)
2009 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
2012 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2015 def_bool $(as-instr,.arch_extension rcpc)
2045 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
2052 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2063 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2106 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2122 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2126 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2142 architectural support for run-time, always-on detection of
2144 to eliminate vulnerabilities arising from memory-unsafe
2152 not be allowed a late bring-up.
2158 Documentation/arch/arm64/memory-tagging-extension.rst.
2170 Access Never to be used with Execute-only mappings.
2177 def_bool $(as-instr,.arch_extension mops)
2189 enforcing page-based protections, but without requiring modification
2192 For details, see Documentation/core-api/protection-keys.rst
2263 If you need the kernel to boot on SVE-capable hardware with broken
2282 bool "Support for NMI-like interrupts"
2285 Adds support for mimicking Non-Maskable Interrupts through the use of
2328 random u64 value in /chosen/kaslr-seed at kernel entry.
2355 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2363 …# needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea…
2396 Provide a set of default command-line options at build time by
2411 Uses the command-line options passed by the boot loader. If
2421 command-line options your boot loader passes to the kernel.
2443 by UEFI firmware (such as non-volatile variables, realtime
2468 continue to boot on existing non-UEFI platforms.