1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_HAS_PMD_SOFTLEAVES if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CC_PLATFORM 23 select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_LAZY_MMU_MODE 38 select ARCH_HAS_MEMBARRIER_SYNC_CORE 39 select ARCH_HAS_MEM_ENCRYPT 40 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS 41 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 42 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 43 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 44 select ARCH_HAS_PREEMPT_LAZY 45 select ARCH_HAS_PTDUMP 46 select ARCH_HAS_PTE_SPECIAL 47 select ARCH_HAS_HW_PTE_YOUNG 48 select ARCH_HAS_SETUP_DMA_OPS 49 select ARCH_HAS_SET_DIRECT_MAP 50 select ARCH_HAS_SET_MEMORY 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_BATCHED_DMA_SYNC 58 select ARCH_HAS_SYSCALL_WRAPPER 59 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 60 select ARCH_HAS_ZONE_DMA_SET if EXPERT 61 select ARCH_HAVE_ELF_PROT 62 select ARCH_HAVE_NMI_SAFE_CMPXCHG 63 select ARCH_HAVE_TRACE_MMIO_ACCESS 64 select ARCH_KEEP_MEMBLOCK 65 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 66 select ARCH_USE_CMPXCHG_LOCKREF 67 select ARCH_USE_GNU_PROPERTY 68 select ARCH_USE_MEMTEST 69 select ARCH_USE_QUEUED_RWLOCKS 70 select ARCH_USE_QUEUED_SPINLOCKS 71 select ARCH_USE_SYM_ANNOTATIONS 72 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 73 select ARCH_SUPPORTS_HUGETLBFS 74 select ARCH_SUPPORTS_MEMORY_FAILURE 75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 76 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 77 select ARCH_SUPPORTS_LTO_CLANG_THIN 78 select ARCH_SUPPORTS_CFI 79 select ARCH_SUPPORTS_ATOMIC_RMW 80 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 81 select ARCH_HAS_PTE_PROTNONE 82 select ARCH_SUPPORTS_NUMA_BALANCING 83 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 84 select ARCH_SUPPORTS_PER_VMA_LOCK 85 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 86 select ARCH_SUPPORTS_RT 87 select ARCH_SUPPORTS_SCHED_SMT 88 select ARCH_SUPPORTS_SCHED_CLUSTER 89 select ARCH_SUPPORTS_SCHED_MC 90 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 91 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 92 select ARCH_WANT_DEFAULT_BPF_JIT 93 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 94 select ARCH_WANT_FRAME_POINTERS 95 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 96 select ARCH_WANT_LD_ORPHAN_WARN 97 select ARCH_WANTS_EXECMEM_LATE 98 select ARCH_WANTS_NO_INSTR 99 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 100 select ARCH_HAS_UBSAN 101 select ARM_AMBA 102 select ARM_ARCH_TIMER 103 select ARM_GIC 104 select AUDIT_ARCH_COMPAT_GENERIC 105 select ARM_GIC_V2M if PCI 106 select ARM_GIC_V3 107 select ARM_GIC_V3_ITS if PCI 108 select ARM_GIC_V5 109 select ARM_PSCI_FW 110 select BUILDTIME_TABLE_SORT 111 select CLONE_BACKWARDS 112 select COMMON_CLK 113 select CPU_PM if (SUSPEND || CPU_IDLE) 114 select CPUMASK_OFFSTACK if NR_CPUS > 256 115 select DCACHE_WORD_ACCESS 116 select HAVE_EXTRA_IPI_TRACEPOINTS 117 select DYNAMIC_FTRACE if FUNCTION_TRACER 118 select DMA_BOUNCE_UNALIGNED_KMALLOC 119 select DMA_DIRECT_REMAP 120 select EDAC_SUPPORT 121 select FRAME_POINTER 122 select FUNCTION_ALIGNMENT_4B 123 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 124 select GENERIC_ALLOCATOR 125 select GENERIC_ARCH_TOPOLOGY 126 select GENERIC_CLOCKEVENTS_BROADCAST 127 select GENERIC_CPU_AUTOPROBE 128 select GENERIC_CPU_CACHE_MAINTENANCE 129 select GENERIC_CPU_DEVICES 130 select GENERIC_CPU_VULNERABILITIES 131 select GENERIC_EARLY_IOREMAP 132 select GENERIC_IDLE_POLL_SETUP 133 select GENERIC_IOREMAP 134 select GENERIC_IRQ_ENTRY 135 select GENERIC_IRQ_IPI 136 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 137 select GENERIC_IRQ_PROBE 138 select GENERIC_IRQ_SHOW 139 select GENERIC_IRQ_SHOW_LEVEL 140 select GENERIC_LIB_DEVMEM_IS_ALLOWED 141 select GENERIC_PCI_IOMAP 142 select GENERIC_SCHED_CLOCK 143 select GENERIC_SMP_IDLE_THREAD 144 select GENERIC_GETTIMEOFDAY 145 select HARDIRQS_SW_RESEND 146 select HAS_IOPORT 147 select HAVE_MOVE_PMD 148 select HAVE_MOVE_PUD 149 select HAVE_PCI 150 select HAVE_ACPI_APEI if (ACPI && EFI) 151 select HAVE_ALIGNED_STRUCT_PAGE 152 select HAVE_ARCH_AUDITSYSCALL 153 select HAVE_ARCH_BITREVERSE if BITREVERSE 154 select HAVE_ARCH_COMPILER_H 155 select HAVE_ARCH_HUGE_VMALLOC 156 select HAVE_ARCH_HUGE_VMAP 157 select HAVE_ARCH_JUMP_LABEL 158 select HAVE_ARCH_JUMP_LABEL_RELATIVE 159 select HAVE_ARCH_KASAN 160 select HAVE_ARCH_KASAN_VMALLOC 161 select HAVE_ARCH_KASAN_SW_TAGS 162 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 163 # Some instrumentation may be unsound, hence EXPERT 164 select HAVE_ARCH_KCSAN if EXPERT 165 select HAVE_ARCH_KFENCE 166 select HAVE_ARCH_KGDB 167 select HAVE_ARCH_KSTACK_ERASE 168 select HAVE_ARCH_MMAP_RND_BITS 169 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 170 select HAVE_ARCH_PREL32_RELOCATIONS 171 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 172 select HAVE_ARCH_SECCOMP_FILTER 173 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 174 select HAVE_ARCH_TRACEHOOK 175 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 176 select HAVE_ARCH_VMAP_STACK 177 select HAVE_ARM_SMCCC 178 select HAVE_ASM_MODVERSIONS 179 select HAVE_EBPF_JIT 180 select HAVE_C_RECORDMCOUNT 181 select HAVE_CMPXCHG_DOUBLE 182 select HAVE_CMPXCHG_LOCAL 183 select HAVE_CONTEXT_TRACKING_USER 184 select HAVE_DEBUG_KMEMLEAK 185 select HAVE_DMA_CONTIGUOUS 186 select HAVE_DYNAMIC_FTRACE 187 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 188 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 189 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 190 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 191 if DYNAMIC_FTRACE_WITH_ARGS 192 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 193 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI && \ 194 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 195 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 196 if DYNAMIC_FTRACE_WITH_ARGS 197 select HAVE_SAMPLE_FTRACE_DIRECT 198 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 199 select HAVE_BUILDTIME_MCOUNT_SORT 200 select HAVE_EFFICIENT_UNALIGNED_ACCESS 201 select HAVE_GUP_FAST 202 select HAVE_FTRACE_GRAPH_FUNC 203 select HAVE_FUNCTION_TRACER 204 select HAVE_FUNCTION_ERROR_INJECTION 205 select HAVE_FUNCTION_GRAPH_FREGS 206 select HAVE_FUNCTION_GRAPH_TRACER 207 select HAVE_GCC_PLUGINS 208 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 209 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 210 select HAVE_HW_BREAKPOINT if PERF_EVENTS 211 select HAVE_IOREMAP_PROT 212 select HAVE_IRQ_TIME_ACCOUNTING 213 select HAVE_LIVEPATCH 214 select HAVE_MOD_ARCH_SPECIFIC 215 select HAVE_NMI 216 select HAVE_PERF_EVENTS 217 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 218 select HAVE_PERF_REGS 219 select HAVE_PERF_USER_STACK_DUMP 220 select HAVE_PREEMPT_DYNAMIC_KEY 221 select HAVE_REGS_AND_STACK_ACCESS_API 222 select HAVE_RELIABLE_STACKTRACE 223 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 224 select HAVE_FUNCTION_ARG_ACCESS_API 225 select MMU_GATHER_RCU_TABLE_FREE 226 select HAVE_RSEQ 227 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 228 select HAVE_STACKPROTECTOR 229 select HAVE_STATIC_CALL if CFI 230 select HAVE_SYSCALL_TRACEPOINTS 231 select HAVE_KPROBES 232 select HAVE_KRETPROBES 233 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 234 select HOTPLUG_SMT if HOTPLUG_CPU 235 select IRQ_DOMAIN 236 select IRQ_FORCED_THREADING 237 select JUMP_LABEL 238 select KASAN_VMALLOC if KASAN 239 select LOCK_MM_AND_FIND_VMA 240 select MODULES_USE_ELF_RELA 241 select NEED_DMA_MAP_STATE 242 select NEED_SG_DMA_LENGTH 243 select OF 244 select OF_EARLY_FLATTREE 245 select PCI_DOMAINS_GENERIC if PCI 246 select PCI_ECAM if (ACPI && PCI) 247 select PCI_SYSCALL if PCI 248 select POWER_RESET 249 select POWER_SUPPLY 250 select HAS_SEPARATE_PREEMPT_RESCHED_BITS 251 select SPARSE_IRQ 252 select SWIOTLB 253 select SYSCTL_EXCEPTION_TRACE 254 select THREAD_INFO_IN_TASK 255 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 256 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 257 select TRACE_IRQFLAGS_SUPPORT 258 select TRACE_IRQFLAGS_NMI_SUPPORT 259 select HAVE_SOFTIRQ_ON_OWN_STACK 260 select USER_STACKTRACE_SUPPORT 261 select VDSO_GETRANDOM 262 select VMAP_STACK 263 help 264 ARM 64-bit (AArch64) Linux support. 265 266config RUSTC_SUPPORTS_ARM64 267 def_bool y 268 depends on CPU_LITTLE_ENDIAN 269 270config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 271 def_bool CC_IS_CLANG 272 # https://github.com/ClangBuiltLinux/linux/issues/1507 273 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 274 275config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 276 def_bool CC_IS_GCC 277 depends on $(cc-option,-fpatchable-function-entry=2) 278 279config 64BIT 280 def_bool y 281 282config MMU 283 def_bool y 284 285config ARM64_CONT_PTE_SHIFT 286 int 287 default 5 if PAGE_SIZE_64KB 288 default 7 if PAGE_SIZE_16KB 289 default 4 290 291config ARM64_CONT_PMD_SHIFT 292 int 293 default 5 if PAGE_SIZE_64KB 294 default 5 if PAGE_SIZE_16KB 295 default 4 296 297config ARCH_MMAP_RND_BITS_MIN 298 default 14 if PAGE_SIZE_64KB 299 default 16 if PAGE_SIZE_16KB 300 default 18 301 302# max bits determined by the following formula: 303# VA_BITS - PTDESC_TABLE_SHIFT 304config ARCH_MMAP_RND_BITS_MAX 305 default 19 if ARM64_VA_BITS=36 306 default 24 if ARM64_VA_BITS=39 307 default 27 if ARM64_VA_BITS=42 308 default 30 if ARM64_VA_BITS=47 309 default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES 310 default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES 311 default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) 312 default 14 if ARM64_64K_PAGES 313 default 16 if ARM64_16K_PAGES 314 default 18 315 316config ARCH_MMAP_RND_COMPAT_BITS_MIN 317 default 7 if ARM64_64K_PAGES 318 default 9 if ARM64_16K_PAGES 319 default 11 320 321config ARCH_MMAP_RND_COMPAT_BITS_MAX 322 default 16 323 324config NO_IOPORT_MAP 325 def_bool y if !PCI 326 327config STACKTRACE_SUPPORT 328 def_bool y 329 330config ILLEGAL_POINTER_VALUE 331 hex 332 default 0xdead000000000000 333 334config LOCKDEP_SUPPORT 335 def_bool y 336 337config GENERIC_BUG 338 def_bool y 339 depends on BUG 340 341config GENERIC_BUG_RELATIVE_POINTERS 342 def_bool y 343 depends on GENERIC_BUG 344 345config GENERIC_HWEIGHT 346 def_bool y 347 348config GENERIC_CSUM 349 def_bool y 350 351config GENERIC_CALIBRATE_DELAY 352 def_bool y 353 354config SMP 355 def_bool y 356 357config KERNEL_MODE_NEON 358 def_bool y 359 360config FIX_EARLYCON_MEM 361 def_bool y 362 363config PGTABLE_LEVELS 364 int 365 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 366 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 367 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 368 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 369 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 370 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 371 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 372 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 373 374config ARCH_SUPPORTS_UPROBES 375 def_bool y 376 377config ARCH_PROC_KCORE_TEXT 378 def_bool y 379 380config BROKEN_GAS_INST 381 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 382 383config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 384 bool 385 # Clang's __builtin_return_address() strips the PAC since 12.0.0 386 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 387 default y if CC_IS_CLANG 388 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 389 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 390 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 391 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 392 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 393 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 394 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 395 default n 396 397config KASAN_SHADOW_OFFSET 398 hex 399 depends on KASAN_GENERIC || KASAN_SW_TAGS 400 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 401 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 402 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 403 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 404 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 405 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 406 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 407 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 408 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 409 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 410 default 0xffffffffffffffff 411 412config UNWIND_TABLES 413 bool 414 415source "arch/arm64/Kconfig.platforms" 416 417menu "Kernel Features" 418 419menu "ARM errata workarounds via the alternatives framework" 420 421config AMPERE_ERRATUM_AC03_CPU_38 422 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 423 default y 424 help 425 This option adds an alternative code sequence to work around Ampere 426 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 427 428 The affected design reports FEAT_HAFDBS as not implemented in 429 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 430 as required by the architecture. The unadvertised HAFDBS 431 implementation suffers from an additional erratum where hardware 432 A/D updates can occur after a PTE has been marked invalid. 433 434 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 435 which avoids enabling unadvertised hardware Access Flag management 436 at stage-2. 437 438 If unsure, say Y. 439 440config AMPERE_ERRATUM_AC04_CPU_23 441 bool "AmpereOne: AC04_CPU_23: Failure to synchronize writes to HCR_EL2 may corrupt address translations." 442 default y 443 help 444 This option adds an alternative code sequence to work around Ampere 445 errata AC04_CPU_23 on AmpereOne. 446 447 Updates to HCR_EL2 can rarely corrupt simultaneous translations for 448 data addresses initiated by load/store instructions. Only 449 instruction initiated translations are vulnerable, not translations 450 from prefetches for example. A DSB before the store to HCR_EL2 is 451 sufficient to prevent older instructions from hitting the window 452 for corruption, and an ISB after is sufficient to prevent younger 453 instructions from hitting the window for corruption. 454 455 If unsure, say Y. 456 457config ARM64_WORKAROUND_CLEAN_CACHE 458 bool 459 460config ARM64_ERRATUM_826319 461 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 462 default y 463 select ARM64_WORKAROUND_CLEAN_CACHE 464 help 465 This option adds an alternative code sequence to work around ARM 466 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 467 AXI master interface and an L2 cache. 468 469 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 470 and is unable to accept a certain write via this interface, it will 471 not progress on read data presented on the read data channel and the 472 system can deadlock. 473 474 The workaround promotes data cache clean instructions to 475 data cache clean-and-invalidate. 476 Please note that this does not necessarily enable the workaround, 477 as it depends on the alternative framework, which will only patch 478 the kernel if an affected CPU is detected. 479 480 If unsure, say Y. 481 482config ARM64_ERRATUM_827319 483 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 484 default y 485 select ARM64_WORKAROUND_CLEAN_CACHE 486 help 487 This option adds an alternative code sequence to work around ARM 488 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 489 master interface and an L2 cache. 490 491 Under certain conditions this erratum can cause a clean line eviction 492 to occur at the same time as another transaction to the same address 493 on the AMBA 5 CHI interface, which can cause data corruption if the 494 interconnect reorders the two transactions. 495 496 The workaround promotes data cache clean instructions to 497 data cache clean-and-invalidate. 498 Please note that this does not necessarily enable the workaround, 499 as it depends on the alternative framework, which will only patch 500 the kernel if an affected CPU is detected. 501 502 If unsure, say Y. 503 504config ARM64_ERRATUM_824069 505 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 506 default y 507 select ARM64_WORKAROUND_CLEAN_CACHE 508 help 509 This option adds an alternative code sequence to work around ARM 510 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 511 to a coherent interconnect. 512 513 If a Cortex-A53 processor is executing a store or prefetch for 514 write instruction at the same time as a processor in another 515 cluster is executing a cache maintenance operation to the same 516 address, then this erratum might cause a clean cache line to be 517 incorrectly marked as dirty. 518 519 The workaround promotes data cache clean instructions to 520 data cache clean-and-invalidate. 521 Please note that this option does not necessarily enable the 522 workaround, as it depends on the alternative framework, which will 523 only patch the kernel if an affected CPU is detected. 524 525 If unsure, say Y. 526 527config ARM64_ERRATUM_819472 528 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 529 default y 530 select ARM64_WORKAROUND_CLEAN_CACHE 531 help 532 This option adds an alternative code sequence to work around ARM 533 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 534 present when it is connected to a coherent interconnect. 535 536 If the processor is executing a load and store exclusive sequence at 537 the same time as a processor in another cluster is executing a cache 538 maintenance operation to the same address, then this erratum might 539 cause data corruption. 540 541 The workaround promotes data cache clean instructions to 542 data cache clean-and-invalidate. 543 Please note that this does not necessarily enable the workaround, 544 as it depends on the alternative framework, which will only patch 545 the kernel if an affected CPU is detected. 546 547 If unsure, say Y. 548 549config ARM64_ERRATUM_832075 550 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 551 default y 552 help 553 This option adds an alternative code sequence to work around ARM 554 erratum 832075 on Cortex-A57 parts up to r1p2. 555 556 Affected Cortex-A57 parts might deadlock when exclusive load/store 557 instructions to Write-Back memory are mixed with Device loads. 558 559 The workaround is to promote device loads to use Load-Acquire 560 semantics. 561 Please note that this does not necessarily enable the workaround, 562 as it depends on the alternative framework, which will only patch 563 the kernel if an affected CPU is detected. 564 565 If unsure, say Y. 566 567config ARM64_ERRATUM_834220 568 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 569 depends on KVM 570 help 571 This option adds an alternative code sequence to work around ARM 572 erratum 834220 on Cortex-A57 parts up to r1p2. 573 574 Affected Cortex-A57 parts might report a Stage 2 translation 575 fault as the result of a Stage 1 fault for load crossing a 576 page boundary when there is a permission or device memory 577 alignment fault at Stage 1 and a translation fault at Stage 2. 578 579 The workaround is to verify that the Stage 1 translation 580 doesn't generate a fault before handling the Stage 2 fault. 581 Please note that this does not necessarily enable the workaround, 582 as it depends on the alternative framework, which will only patch 583 the kernel if an affected CPU is detected. 584 585 If unsure, say N. 586 587config ARM64_ERRATUM_1742098 588 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 589 depends on COMPAT 590 default y 591 help 592 This option removes the AES hwcap for aarch32 user-space to 593 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 594 595 Affected parts may corrupt the AES state if an interrupt is 596 taken between a pair of AES instructions. These instructions 597 are only present if the cryptography extensions are present. 598 All software should have a fallback implementation for CPUs 599 that don't implement the cryptography extensions. 600 601 If unsure, say Y. 602 603config ARM64_ERRATUM_845719 604 bool "Cortex-A53: 845719: a load might read incorrect data" 605 depends on COMPAT 606 default y 607 help 608 This option adds an alternative code sequence to work around ARM 609 erratum 845719 on Cortex-A53 parts up to r0p4. 610 611 When running a compat (AArch32) userspace on an affected Cortex-A53 612 part, a load at EL0 from a virtual address that matches the bottom 32 613 bits of the virtual address used by a recent load at (AArch64) EL1 614 might return incorrect data. 615 616 The workaround is to write the contextidr_el1 register on exception 617 return to a 32-bit task. 618 Please note that this does not necessarily enable the workaround, 619 as it depends on the alternative framework, which will only patch 620 the kernel if an affected CPU is detected. 621 622 If unsure, say Y. 623 624config ARM64_ERRATUM_843419 625 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 626 default y 627 help 628 This option links the kernel with '--fix-cortex-a53-843419' and 629 enables PLT support to replace certain ADRP instructions, which can 630 cause subsequent memory accesses to use an incorrect address on 631 Cortex-A53 parts up to r0p4. 632 633 If unsure, say Y. 634 635config ARM64_ERRATUM_1024718 636 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 637 default y 638 help 639 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 640 641 Affected Cortex-A55 cores (all revisions) could cause incorrect 642 update of the hardware dirty bit when the DBM/AP bits are updated 643 without a break-before-make. The workaround is to disable the usage 644 of hardware DBM locally on the affected cores. CPUs not affected by 645 this erratum will continue to use the feature. 646 647 If unsure, say Y. 648 649config ARM64_ERRATUM_1418040 650 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 651 default y 652 depends on COMPAT 653 help 654 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 655 errata 1188873 and 1418040. 656 657 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 658 cause register corruption when accessing the timer registers 659 from AArch32 userspace. 660 661 If unsure, say Y. 662 663config ARM64_WORKAROUND_SPECULATIVE_AT 664 bool 665 666config ARM64_ERRATUM_1165522 667 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 668 default y 669 select ARM64_WORKAROUND_SPECULATIVE_AT 670 help 671 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 672 673 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 674 corrupted TLBs by speculating an AT instruction during a guest 675 context switch. 676 677 If unsure, say Y. 678 679config ARM64_ERRATUM_1319367 680 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 681 default y 682 select ARM64_WORKAROUND_SPECULATIVE_AT 683 help 684 This option adds work arounds for ARM Cortex-A57 erratum 1319537 685 and A72 erratum 1319367 686 687 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 688 speculating an AT instruction during a guest context switch. 689 690 If unsure, say Y. 691 692config ARM64_ERRATUM_1530923 693 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 694 default y 695 select ARM64_WORKAROUND_SPECULATIVE_AT 696 help 697 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 698 699 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 700 corrupted TLBs by speculating an AT instruction during a guest 701 context switch. 702 703 If unsure, say Y. 704 705config ARM64_WORKAROUND_REPEAT_TLBI_SYNC 706 bool 707 # This workaround is (only) suitable for TLB invalidation errata where 708 # all of the following conditions are true: 709 # 710 # - The effects of the errata are only a loss of ordering/completion 711 # for explicit memory accesses when the TLBI is completed with a DSB. 712 # The removal of TLB entries is not affected. 713 # 714 # Note that architecturally, S2-only invalidation does not remove 715 # combined S1+S2 entries, and does not complete accesses translated 716 # via those S1+S2 entries. Consequently, where this condition holds, 717 # the errata do not affect S2-only invalidation. 718 # 719 # - The errata only affect broadcast TLB invalidation operations (e.g. 720 # TLBI VMALLE1IS), and do not affect local TLB invalidation 721 # operations (e.g. TLBI VMALLE1). 722 # 723 # - After any number of affected TLBI operations are completed with a 724 # DSB, the errata can be mitigated by executing a single arbitrary 725 # broadcast TLBI (which targets an arbitrary translation regime), 726 # followed by a DSB. 727 # 728 # For more rationale, see commit a8f78680ee6bf795. 729 730config ARM64_ERRATUM_2441007 731 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 732 select ARM64_WORKAROUND_REPEAT_TLBI_SYNC 733 help 734 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 735 736 Under very rare circumstances, affected Cortex-A55 CPUs 737 may not handle a race between a break-before-make sequence on one 738 CPU, and another CPU accessing the same page. This could allow a 739 store to a page that has been unmapped. 740 741 Work around this by adding the affected CPUs to the list that needs 742 TLB sequences to be done twice. 743 744 If unsure, say N. 745 746config ARM64_ERRATUM_1286807 747 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 748 select ARM64_WORKAROUND_REPEAT_TLBI_SYNC 749 help 750 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 751 752 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 753 address for a cacheable mapping of a location is being 754 accessed by a core while another core is remapping the virtual 755 address to a new physical page using the recommended 756 break-before-make sequence, then under very rare circumstances 757 TLBI+DSB completes before a read using the translation being 758 invalidated has been observed by other observers. The 759 workaround repeats the TLBI+DSB operation. 760 761 If unsure, say N. 762 763config ARM64_ERRATUM_1463225 764 bool "Cortex-A76: Software Step might prevent interrupt recognition" 765 default y 766 help 767 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 768 769 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 770 of a system call instruction (SVC) can prevent recognition of 771 subsequent interrupts when software stepping is disabled in the 772 exception handler of the system call and either kernel debugging 773 is enabled or VHE is in use. 774 775 Work around the erratum by triggering a dummy step exception 776 when handling a system call from a task that is being stepped 777 in a VHE configuration of the kernel. 778 779 If unsure, say Y. 780 781config ARM64_ERRATUM_1542419 782 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 783 help 784 This option adds a workaround for ARM Neoverse-N1 erratum 785 1542419. 786 787 Affected Neoverse-N1 cores could execute a stale instruction when 788 modified by another CPU. The workaround depends on a firmware 789 counterpart. 790 791 Workaround the issue by hiding the DIC feature from EL0. This 792 forces user-space to perform cache maintenance. 793 794 If unsure, say N. 795 796config ARM64_ERRATUM_1508412 797 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 798 default y 799 help 800 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 801 802 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 803 of a store-exclusive or read of PAR_EL1 and a load with device or 804 non-cacheable memory attributes. The workaround depends on a firmware 805 counterpart. 806 807 KVM guests must also have the workaround implemented or they can 808 deadlock the system. 809 810 Work around the issue by inserting DMB SY barriers around PAR_EL1 811 register reads and warning KVM users. The DMB barrier is sufficient 812 to prevent a speculative PAR_EL1 read. 813 814 If unsure, say Y. 815 816config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 817 bool 818 819config ARM64_ERRATUM_2051678 820 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 821 default y 822 help 823 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 824 Affected Cortex-A510 might not respect the ordering rules for 825 hardware update of the page table's dirty bit. The workaround 826 is to not enable the feature on affected CPUs. 827 828 If unsure, say Y. 829 830config ARM64_ERRATUM_2077057 831 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 832 default y 833 help 834 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 835 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 836 expected, but a Pointer Authentication trap is taken instead. The 837 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 838 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 839 840 This can only happen when EL2 is stepping EL1. 841 842 When these conditions occur, the SPSR_EL2 value is unchanged from the 843 previous guest entry, and can be restored from the in-memory copy. 844 845 If unsure, say Y. 846 847config ARM64_ERRATUM_2658417 848 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 849 default y 850 help 851 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 852 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 853 BFMMLA or VMMLA instructions in rare circumstances when a pair of 854 A510 CPUs are using shared neon hardware. As the sharing is not 855 discoverable by the kernel, hide the BF16 HWCAP to indicate that 856 user-space should not be using these instructions. 857 858 If unsure, say Y. 859 860config ARM64_ERRATUM_2119858 861 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 862 default y 863 depends on CORESIGHT_TRBE 864 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 865 help 866 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 867 868 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 869 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 870 the event of a WRAP event. 871 872 Work around the issue by always making sure we move the TRBPTR_EL1 by 873 256 bytes before enabling the buffer and filling the first 256 bytes of 874 the buffer with ETM ignore packets upon disabling. 875 876 If unsure, say Y. 877 878config ARM64_ERRATUM_2139208 879 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 880 default y 881 depends on CORESIGHT_TRBE 882 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 883 help 884 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 885 886 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 887 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 888 the event of a WRAP event. 889 890 Work around the issue by always making sure we move the TRBPTR_EL1 by 891 256 bytes before enabling the buffer and filling the first 256 bytes of 892 the buffer with ETM ignore packets upon disabling. 893 894 If unsure, say Y. 895 896config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 897 bool 898 899config ARM64_ERRATUM_2054223 900 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 901 default y 902 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 903 help 904 Enable workaround for ARM Cortex-A710 erratum 2054223 905 906 Affected cores may fail to flush the trace data on a TSB instruction, when 907 the PE is in trace prohibited state. This will cause losing a few bytes 908 of the trace cached. 909 910 Workaround is to issue two TSB consecutively on affected cores. 911 912 If unsure, say Y. 913 914config ARM64_ERRATUM_2067961 915 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 916 default y 917 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 918 help 919 Enable workaround for ARM Neoverse-N2 erratum 2067961 920 921 Affected cores may fail to flush the trace data on a TSB instruction, when 922 the PE is in trace prohibited state. This will cause losing a few bytes 923 of the trace cached. 924 925 Workaround is to issue two TSB consecutively on affected cores. 926 927 If unsure, say Y. 928 929config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 930 bool 931 932config ARM64_ERRATUM_2253138 933 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 934 depends on CORESIGHT_TRBE 935 default y 936 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 937 help 938 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 939 940 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 941 for TRBE. Under some conditions, the TRBE might generate a write to the next 942 virtually addressed page following the last page of the TRBE address space 943 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 944 945 Work around this in the driver by always making sure that there is a 946 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 947 948 If unsure, say Y. 949 950config ARM64_ERRATUM_2224489 951 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 952 depends on CORESIGHT_TRBE 953 default y 954 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 955 help 956 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 957 958 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 959 for TRBE. Under some conditions, the TRBE might generate a write to the next 960 virtually addressed page following the last page of the TRBE address space 961 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 962 963 Work around this in the driver by always making sure that there is a 964 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 965 966 If unsure, say Y. 967 968config ARM64_ERRATUM_2441009 969 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 970 select ARM64_WORKAROUND_REPEAT_TLBI_SYNC 971 help 972 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 973 974 Under very rare circumstances, affected Cortex-A510 CPUs 975 may not handle a race between a break-before-make sequence on one 976 CPU, and another CPU accessing the same page. This could allow a 977 store to a page that has been unmapped. 978 979 Work around this by adding the affected CPUs to the list that needs 980 TLB sequences to be done twice. 981 982 If unsure, say N. 983 984config ARM64_ERRATUM_2064142 985 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 986 depends on CORESIGHT_TRBE 987 default y 988 help 989 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 990 991 Affected Cortex-A510 core might fail to write into system registers after the 992 TRBE has been disabled. Under some conditions after the TRBE has been disabled 993 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 994 and TRBTRG_EL1 will be ignored and will not be effected. 995 996 Work around this in the driver by executing TSB CSYNC and DSB after collection 997 is stopped and before performing a system register write to one of the affected 998 registers. 999 1000 If unsure, say Y. 1001 1002config ARM64_ERRATUM_2038923 1003 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 1004 depends on CORESIGHT_TRBE 1005 default y 1006 help 1007 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 1008 1009 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 1010 prohibited within the CPU. As a result, the trace buffer or trace buffer state 1011 might be corrupted. This happens after TRBE buffer has been enabled by setting 1012 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 1013 execution changes from a context, in which trace is prohibited to one where it 1014 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1015 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1016 the trace buffer state might be corrupted. 1017 1018 Work around this in the driver by preventing an inconsistent view of whether the 1019 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1020 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1021 two ISB instructions if no ERET is to take place. 1022 1023 If unsure, say Y. 1024 1025config ARM64_ERRATUM_1902691 1026 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1027 depends on CORESIGHT_TRBE 1028 default y 1029 help 1030 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1031 1032 Affected Cortex-A510 core might cause trace data corruption, when being written 1033 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1034 trace data. 1035 1036 Work around this problem in the driver by just preventing TRBE initialization on 1037 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1038 on such implementations. This will cover the kernel for any firmware that doesn't 1039 do this already. 1040 1041 If unsure, say Y. 1042 1043config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT 1044 bool 1045 # Targeting errata affecting AMEVCNTR01, the AMU constant counter. 1046 # On affected CPUs the counter may not increment at the expected rate, 1047 # making it unreliable. As a result, AMU users should treat it as 1048 # unavailable rather than relying on misleading counter values. 1049 1050config ARM64_ERRATUM_2457168 1051 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1052 depends on ARM64_AMU_EXTN 1053 select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT 1054 default y 1055 help 1056 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1057 1058 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1059 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1060 incorrectly giving a significantly higher output value. 1061 1062 Work around this problem by returning 0 when reading the affected counter in 1063 key locations that results in disabling all users of this counter. This effect 1064 is the same to firmware disabling affected counters. 1065 1066 If unsure, say Y. 1067 1068config ARM64_ERRATUM_2645198 1069 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1070 default y 1071 help 1072 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1073 1074 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1075 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1076 next instruction abort caused by permission fault. 1077 1078 Only user-space does executable to non-executable permission transition via 1079 mprotect() system call. Workaround the problem by doing a break-before-make 1080 TLB invalidation, for all changes to executable user space mappings. 1081 1082 If unsure, say Y. 1083 1084config ARM64_ERRATUM_3821522 1085 bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" 1086 depends on ARM64_AMU_EXTN 1087 select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT 1088 default y 1089 help 1090 This option adds the workaround for ARM Cortex-A725 erratum 3821522. 1091 1092 On affected A725 cores, the CNT_CYCLES event may incur a significant 1093 increment error when entering and subsequently exiting WFx. 1094 As a result, the CNT_CYCLES may diverge from the system counter 1095 frequency at which it is expected to increment. 1096 This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, 1097 being unreliable and unsuitable for use. 1098 1099 Since there is no hardware workaround, reads of the affected CNT_CYCLES 1100 counter return 0 in the relevant paths. This causes users of the counter 1101 to treat it as unavailable and is functionally equivalent to firmware 1102 disabling the affected counter. 1103 1104 If unsure, say Y. 1105 1106config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1107 bool 1108 1109config ARM64_ERRATUM_2966298 1110 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1111 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1112 default y 1113 help 1114 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1115 1116 On an affected Cortex-A520 core, a speculatively executed unprivileged 1117 load might leak data from a privileged level via a cache side channel. 1118 1119 Work around this problem by executing a TLBI before returning to EL0. 1120 1121 If unsure, say Y. 1122 1123config ARM64_ERRATUM_3117295 1124 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1125 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1126 default y 1127 help 1128 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1129 1130 On an affected Cortex-A510 core, a speculatively executed unprivileged 1131 load might leak data from a privileged level via a cache side channel. 1132 1133 Work around this problem by executing a TLBI before returning to EL0. 1134 1135 If unsure, say Y. 1136 1137config ARM64_ERRATUM_3194386 1138 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1139 default y 1140 help 1141 This option adds the workaround for the following errata: 1142 1143 * ARM Cortex-A76 erratum 3324349 1144 * ARM Cortex-A77 erratum 3324348 1145 * ARM Cortex-A78 erratum 3324344 1146 * ARM Cortex-A78C erratum 3324346 1147 * ARM Cortex-A78C erratum 3324347 1148 * ARM Cortex-A710 erratam 3324338 1149 * ARM Cortex-A715 errartum 3456084 1150 * ARM Cortex-A720 erratum 3456091 1151 * ARM Cortex-A725 erratum 3456106 1152 * ARM Cortex-X1 erratum 3324344 1153 * ARM Cortex-X1C erratum 3324346 1154 * ARM Cortex-X2 erratum 3324338 1155 * ARM Cortex-X3 erratum 3324335 1156 * ARM Cortex-X4 erratum 3194386 1157 * ARM Cortex-X925 erratum 3324334 1158 * ARM Neoverse-N1 erratum 3324349 1159 * ARM Neoverse N2 erratum 3324339 1160 * ARM Neoverse-N3 erratum 3456111 1161 * ARM Neoverse-V1 erratum 3324341 1162 * ARM Neoverse V2 erratum 3324336 1163 * ARM Neoverse-V3 erratum 3312417 1164 * ARM Neoverse-V3AE erratum 3312417 1165 1166 On affected cores "MSR SSBS, #0" instructions may not affect 1167 subsequent speculative instructions, which may permit unexepected 1168 speculative store bypassing. 1169 1170 Work around this problem by placing a Speculation Barrier (SB) or 1171 Instruction Synchronization Barrier (ISB) after kernel changes to 1172 SSBS. The presence of the SSBS special-purpose register is hidden 1173 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1174 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1175 1176 If unsure, say Y. 1177 1178config ARM64_ERRATUM_4311569 1179 bool "SI L1: 4311569: workaround for premature CMO completion erratum" 1180 default y 1181 help 1182 This option adds the workaround for ARM SI L1 erratum 4311569. 1183 1184 The erratum of SI L1 can cause an early response to a combined write 1185 and cache maintenance operation (WR+CMO) before the operation is fully 1186 completed to the Point of Serialization (POS). 1187 This can result in a non-I/O coherent agent observing stale data, 1188 potentially leading to system instability or incorrect behavior. 1189 1190 Enabling this option implements a software workaround by inserting a 1191 second loop of Cache Maintenance Operation (CMO) immediately following the 1192 end of function to do CMOs. This ensures that the data is correctly serialized 1193 before the buffer is handed off to a non-coherent agent. 1194 1195 If unsure, say Y. 1196 1197config ARM64_ERRATUM_4193714 1198 bool "C1-Pro: 4193714: SME DVMSync early acknowledgement" 1199 depends on ARM64_SME 1200 default y 1201 help 1202 Enable workaround for C1-Pro acknowledging the DVMSync before 1203 the SME memory accesses are complete. This will cause TLB 1204 maintenance for processes using SME to also issue an IPI to 1205 the affected CPUs. 1206 1207 If unsure, say Y. 1208 1209config ARM64_ERRATUM_4118414 1210 bool "Various: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 1211 default y 1212 select ARM64_WORKAROUND_REPEAT_TLBI_SYNC 1213 help 1214 This option adds a workaround for the following errata: 1215 1216 * ARM C1-Premium erratum 4193780 1217 * ARM C1-Ultra erratum 4193780 1218 * ARM Cortex-A76 erratum 4193800 1219 * ARM Cortex-A76AE erratum 4193801 1220 * ARM Cortex-A77 erratum 4193798 1221 * ARM Cortex-A78 erratum 4193791 1222 * ARM Cortex-A78AE erratum 4193793 1223 * ARM Cortex-A78C erratum 4193794 1224 * ARM Cortex-A710 erratum 4193788 1225 * ARM Cortex-X1 erratum 4193791 1226 * ARM Cortex-X1C erratum 4193792 1227 * ARM Cortex-X2 erratum 4193788 1228 * ARM Cortex-X3 erratum 4193786 1229 * ARM Cortex-X4 erratum 4118414 1230 * ARM Cortex-X925 erratum 4193781 1231 * ARM Neoverse-N1 erratum 4193800 1232 * ARM Neoverse-N2 erratum 4193789 1233 * ARM Neoverse-V1 erratum 4193790 1234 * ARM Neoverse-V2 erratum 4193787 1235 * ARM Neoverse-V3 erratum 4193784 1236 * ARM Neoverse-V3AE erratum 4193784 1237 * Microsoft Azure Cobalt 100 4193789 1238 * NVIDIA Olympus erratum T410-OLY-1029 1239 1240 On affected cores, some memory accesses might not be completed by 1241 broadcast TLB invalidation. 1242 1243 This issue is also known as CVE-2025-10263. 1244 1245 If unsure, say Y. 1246 1247config CAVIUM_ERRATUM_22375 1248 bool "Cavium erratum 22375, 24313" 1249 default y 1250 help 1251 Enable workaround for errata 22375 and 24313. 1252 1253 This implements two gicv3-its errata workarounds for ThunderX. Both 1254 with a small impact affecting only ITS table allocation. 1255 1256 erratum 22375: only alloc 8MB table size 1257 erratum 24313: ignore memory access type 1258 1259 The fixes are in ITS initialization and basically ignore memory access 1260 type and table size provided by the TYPER and BASER registers. 1261 1262 If unsure, say Y. 1263 1264config CAVIUM_ERRATUM_23144 1265 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1266 depends on NUMA 1267 default y 1268 help 1269 ITS SYNC command hang for cross node io and collections/cpu mapping. 1270 1271 If unsure, say Y. 1272 1273config CAVIUM_ERRATUM_23154 1274 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1275 default y 1276 help 1277 The ThunderX GICv3 implementation requires a modified version for 1278 reading the IAR status to ensure data synchronization 1279 (access to icc_iar1_el1 is not sync'ed before and after). 1280 1281 It also suffers from erratum 38545 (also present on Marvell's 1282 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1283 spuriously presented to the CPU interface. 1284 1285 If unsure, say Y. 1286 1287config CAVIUM_ERRATUM_27456 1288 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1289 default y 1290 help 1291 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1292 instructions may cause the icache to become corrupted if it 1293 contains data for a non-current ASID. The fix is to 1294 invalidate the icache when changing the mm context. 1295 1296 If unsure, say Y. 1297 1298config CAVIUM_ERRATUM_30115 1299 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1300 default y 1301 help 1302 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1303 1.2, and T83 Pass 1.0, KVM guest execution may disable 1304 interrupts in host. Trapping both GICv3 group-0 and group-1 1305 accesses sidesteps the issue. 1306 1307 If unsure, say Y. 1308 1309config CAVIUM_TX2_ERRATUM_219 1310 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1311 default y 1312 help 1313 On Cavium ThunderX2, a load, store or prefetch instruction between a 1314 TTBR update and the corresponding context synchronizing operation can 1315 cause a spurious Data Abort to be delivered to any hardware thread in 1316 the CPU core. 1317 1318 Work around the issue by avoiding the problematic code sequence and 1319 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1320 trap handler performs the corresponding register access, skips the 1321 instruction and ensures context synchronization by virtue of the 1322 exception return. 1323 1324 If unsure, say Y. 1325 1326config FUJITSU_ERRATUM_010001 1327 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1328 default y 1329 help 1330 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1331 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1332 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1333 This fault occurs under a specific hardware condition when a 1334 load/store instruction performs an address translation using: 1335 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1336 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1337 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1338 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1339 1340 The workaround is to ensure these bits are clear in TCR_ELx. 1341 The workaround only affects the Fujitsu-A64FX. 1342 1343 If unsure, say Y. 1344 1345config HISILICON_ERRATUM_161600802 1346 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1347 default y 1348 help 1349 The HiSilicon Hip07 SoC uses the wrong redistributor base 1350 when issued ITS commands such as VMOVP and VMAPP, and requires 1351 a 128kB offset to be applied to the target address in this commands. 1352 1353 If unsure, say Y. 1354 1355config HISILICON_ERRATUM_162100801 1356 bool "Hip09 162100801 erratum support" 1357 default y 1358 help 1359 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1360 during unmapping operation, which will cause some vSGIs lost. 1361 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1362 after VMOVP. 1363 1364 If unsure, say Y. 1365 1366config HISILICON_ERRATUM_162100125 1367 bool "Hisilicon erratum 162100125" 1368 default y 1369 select ARM64_WORKAROUND_DISABLE_CNP 1370 help 1371 On HiSilicon HIP09, TLB entry matching behavior when CNP 1372 (TTBRx.CNP=1) is enabled differs from the ARM architecture 1373 specification. 1374 1375 TLB entries may be incorrectly shared between CPUs, potentially 1376 causing TLB conflicts and stale mappings. 1377 1378 Disable CNP support for affected HiSilicon HIP09 cores. 1379 1380 If unsure, say Y. 1381 1382config QCOM_FALKOR_ERRATUM_1003 1383 bool "Falkor E1003: Incorrect translation due to ASID change" 1384 default y 1385 help 1386 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1387 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1388 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1389 then only for entries in the walk cache, since the leaf translation 1390 is unchanged. Work around the erratum by invalidating the walk cache 1391 entries for the trampoline before entering the kernel proper. 1392 1393config QCOM_FALKOR_ERRATUM_1009 1394 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1395 default y 1396 select ARM64_WORKAROUND_REPEAT_TLBI_SYNC 1397 help 1398 On Falkor v1, the CPU may prematurely complete a DSB following a 1399 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1400 one more time to fix the issue. 1401 1402 If unsure, say Y. 1403 1404config QCOM_QDF2400_ERRATUM_0065 1405 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1406 default y 1407 help 1408 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1409 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1410 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1411 1412 If unsure, say Y. 1413 1414config QCOM_FALKOR_ERRATUM_E1041 1415 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1416 default y 1417 help 1418 Falkor CPU may speculatively fetch instructions from an improper 1419 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1420 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1421 1422 If unsure, say Y. 1423 1424config ARM64_WORKAROUND_DISABLE_CNP 1425 bool 1426 1427config NVIDIA_CARMEL_CNP_ERRATUM 1428 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1429 default y 1430 select ARM64_WORKAROUND_DISABLE_CNP 1431 help 1432 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1433 invalidate shared TLB entries installed by a different core, as it would 1434 on standard ARM cores. 1435 1436 If unsure, say Y. 1437 1438config NVIDIA_OLYMPUS_1027_ERRATUM 1439 bool "NVIDIA Olympus: device store/load ordering erratum" 1440 default y 1441 help 1442 This option adds an alternative code sequence to work around an 1443 NVIDIA Olympus core erratum where a Device-nGnR* store can be 1444 observed by a peripheral after a younger Device-nGnR* load to the 1445 same peripheral. This breaks the program order that drivers rely 1446 on for MMIO and can leave a device in an incorrect state. 1447 1448 The workaround inserts a DMB OSH immediately before raw MMIO loads. 1449 The erratum cannot occur when a DMB that orders loads appears 1450 between the store and load, preventing the younger load from being 1451 observed before the older store. 1452 1453 The alternatives framework patches in DMB OSH only when an affected 1454 CPU is detected. Other CPUs execute a NOP in its place. Disabling 1455 this option leaves the original MMIO read instruction stream 1456 unchanged. 1457 1458 If unsure, say Y. 1459 1460config RENESAS_ERRATUM_GEN4GICITS1 1461 bool "Renesas R-Car Gen4: GIC600 can not access physical addresses above 4 GiB" 1462 default y 1463 help 1464 The Renesas R-Car Gen4 S4/V4H/V4M GIC600 SoC integrations have AXI 1465 addressing limited to the first 32-bit of physical address space. 1466 1467 If unsure, say Y. 1468 1469config ROCKCHIP_ERRATUM_3568002 1470 bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" 1471 default y 1472 help 1473 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI 1474 addressing limited to the first 32bit of physical address space. 1475 1476 If unsure, say Y. 1477 1478config ROCKCHIP_ERRATUM_3588001 1479 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1480 default y 1481 help 1482 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1483 This means, that its sharability feature may not be used, even though it 1484 is supported by the IP itself. 1485 1486 If unsure, say Y. 1487 1488config SOCIONEXT_SYNQUACER_PREITS 1489 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1490 default y 1491 help 1492 Socionext Synquacer SoCs implement a separate h/w block to generate 1493 MSI doorbell writes with non-zero values for the device ID. 1494 1495 If unsure, say Y. 1496 1497endmenu # "ARM errata workarounds via the alternatives framework" 1498 1499choice 1500 prompt "Page size" 1501 default ARM64_4K_PAGES 1502 help 1503 Page size (translation granule) configuration. 1504 1505config ARM64_4K_PAGES 1506 bool "4KB" 1507 select HAVE_PAGE_SIZE_4KB 1508 help 1509 This feature enables 4KB pages support. 1510 1511config ARM64_16K_PAGES 1512 bool "16KB" 1513 select HAVE_PAGE_SIZE_16KB 1514 help 1515 The system will use 16KB pages support. AArch32 emulation 1516 requires applications compiled with 16K (or a multiple of 16K) 1517 aligned segments. 1518 1519config ARM64_64K_PAGES 1520 bool "64KB" 1521 select HAVE_PAGE_SIZE_64KB 1522 help 1523 This feature enables 64KB pages support (4KB by default) 1524 allowing only two levels of page tables and faster TLB 1525 look-up. AArch32 emulation requires applications compiled 1526 with 64K aligned segments. 1527 1528endchoice 1529 1530choice 1531 prompt "Virtual address space size" 1532 default ARM64_VA_BITS_52 1533 help 1534 Allows choosing one of multiple possible virtual address 1535 space sizes. The level of translation table is determined by 1536 a combination of page size and virtual address space size. 1537 1538config ARM64_VA_BITS_36 1539 bool "36-bit" if EXPERT 1540 depends on PAGE_SIZE_16KB 1541 1542config ARM64_VA_BITS_39 1543 bool "39-bit" 1544 depends on PAGE_SIZE_4KB 1545 1546config ARM64_VA_BITS_42 1547 bool "42-bit" 1548 depends on PAGE_SIZE_64KB 1549 1550config ARM64_VA_BITS_47 1551 bool "47-bit" 1552 depends on PAGE_SIZE_16KB 1553 1554config ARM64_VA_BITS_48 1555 bool "48-bit" 1556 1557config ARM64_VA_BITS_52 1558 bool "52-bit" 1559 help 1560 Enable 52-bit virtual addressing for userspace when explicitly 1561 requested via a hint to mmap(). The kernel will also use 52-bit 1562 virtual addresses for its own mappings (provided HW support for 1563 this feature is available, otherwise it reverts to 48-bit). 1564 1565 NOTE: Enabling 52-bit virtual addressing in conjunction with 1566 ARMv8.3 Pointer Authentication will result in the PAC being 1567 reduced from 7 bits to 3 bits, which may have a significant 1568 impact on its susceptibility to brute-force attacks. 1569 1570 If unsure, select 48-bit virtual addressing instead. 1571 1572endchoice 1573 1574config ARM64_FORCE_52BIT 1575 bool "Force 52-bit virtual addresses for userspace" 1576 depends on ARM64_VA_BITS_52 && EXPERT 1577 help 1578 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1579 to maintain compatibility with older software by providing 48-bit VAs 1580 unless a hint is supplied to mmap. 1581 1582 This configuration option disables the 48-bit compatibility logic, and 1583 forces all userspace addresses to be 52-bit on HW that supports it. One 1584 should only enable this configuration option for stress testing userspace 1585 memory management code. If unsure say N here. 1586 1587config ARM64_VA_BITS 1588 int 1589 default 36 if ARM64_VA_BITS_36 1590 default 39 if ARM64_VA_BITS_39 1591 default 42 if ARM64_VA_BITS_42 1592 default 47 if ARM64_VA_BITS_47 1593 default 48 if ARM64_VA_BITS_48 1594 default 52 if ARM64_VA_BITS_52 1595 1596choice 1597 prompt "Physical address space size" 1598 default ARM64_PA_BITS_48 1599 help 1600 Choose the maximum physical address range that the kernel will 1601 support. 1602 1603config ARM64_PA_BITS_48 1604 bool "48-bit" 1605 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1606 1607config ARM64_PA_BITS_52 1608 bool "52-bit" 1609 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1610 help 1611 Enable support for a 52-bit physical address space, introduced as 1612 part of the ARMv8.2-LPA extension. 1613 1614 With this enabled, the kernel will also continue to work on CPUs that 1615 do not support ARMv8.2-LPA, but with some added memory overhead (and 1616 minor performance overhead). 1617 1618endchoice 1619 1620config ARM64_PA_BITS 1621 int 1622 default 48 if ARM64_PA_BITS_48 1623 default 52 if ARM64_PA_BITS_52 1624 1625config ARM64_LPA2 1626 def_bool y 1627 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1628 1629choice 1630 prompt "Endianness" 1631 default CPU_LITTLE_ENDIAN 1632 help 1633 Select the endianness of data accesses performed by the CPU. Userspace 1634 applications will need to be compiled and linked for the endianness 1635 that is selected here. 1636 1637config CPU_BIG_ENDIAN 1638 bool "Build big-endian kernel" 1639 depends on BROKEN 1640 help 1641 Say Y if you plan on running a kernel with a big-endian userspace. 1642 1643config CPU_LITTLE_ENDIAN 1644 bool "Build little-endian kernel" 1645 help 1646 Say Y if you plan on running a kernel with a little-endian userspace. 1647 This is usually the case for distributions targeting arm64. 1648 1649endchoice 1650 1651config NR_CPUS 1652 int "Maximum number of CPUs (2-4096)" 1653 range 2 4096 1654 default "512" 1655 1656config HOTPLUG_CPU 1657 bool "Support for hot-pluggable CPUs" 1658 select GENERIC_IRQ_MIGRATION 1659 help 1660 Say Y here to experiment with turning CPUs off and on. CPUs 1661 can be controlled through /sys/devices/system/cpu. 1662 1663# Common NUMA Features 1664config NUMA 1665 bool "NUMA Memory Allocation and Scheduler Support" 1666 select GENERIC_ARCH_NUMA 1667 select OF_NUMA 1668 select HAVE_SETUP_PER_CPU_AREA 1669 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1670 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1671 select USE_PERCPU_NUMA_NODE_ID 1672 help 1673 Enable NUMA (Non-Uniform Memory Access) support. 1674 1675 The kernel will try to allocate memory used by a CPU on the 1676 local memory of the CPU and add some more 1677 NUMA awareness to the kernel. 1678 1679config NODES_SHIFT 1680 int "Maximum NUMA Nodes (as a power of 2)" 1681 range 1 10 1682 default "4" 1683 depends on NUMA 1684 help 1685 Specify the maximum number of NUMA Nodes available on the target 1686 system. Increases memory reserved to accommodate various tables. 1687 1688source "kernel/Kconfig.hz" 1689 1690config ARCH_SPARSEMEM_ENABLE 1691 def_bool y 1692 select SPARSEMEM_VMEMMAP_ENABLE 1693 1694config HW_PERF_EVENTS 1695 def_bool y 1696 depends on ARM_PMU 1697 1698# Supported by clang >= 7.0 or GCC >= 12.0.0 1699config CC_HAVE_SHADOW_CALL_STACK 1700 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1701 1702config PARAVIRT 1703 bool "Enable paravirtualization code" 1704 select HAVE_PV_STEAL_CLOCK_GEN 1705 help 1706 This changes the kernel so it can modify itself when it is run 1707 under a hypervisor, potentially improving performance significantly 1708 over full virtualization. 1709 1710config PARAVIRT_TIME_ACCOUNTING 1711 bool "Paravirtual steal time accounting" 1712 select PARAVIRT 1713 help 1714 Select this option to enable fine granularity task steal time 1715 accounting. Time spent executing other tasks in parallel with 1716 the current vCPU is discounted from the vCPU power. To account for 1717 that, there can be a small performance impact. 1718 1719 If in doubt, say N here. 1720 1721config ARCH_SUPPORTS_KEXEC 1722 def_bool PM_SLEEP_SMP 1723 1724config ARCH_SUPPORTS_KEXEC_FILE 1725 def_bool y 1726 1727config ARCH_SELECTS_KEXEC_FILE 1728 def_bool y 1729 depends on KEXEC_FILE 1730 select HAVE_IMA_KEXEC if IMA 1731 1732config ARCH_SUPPORTS_KEXEC_SIG 1733 def_bool y 1734 1735config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1736 def_bool y 1737 1738config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1739 def_bool y 1740 1741config ARCH_SUPPORTS_KEXEC_HANDOVER 1742 def_bool y 1743 1744config ARCH_SUPPORTS_CRASH_DUMP 1745 def_bool y 1746 1747config ARCH_DEFAULT_CRASH_DUMP 1748 def_bool y 1749 1750config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1751 def_bool CRASH_RESERVE 1752 1753config TRANS_TABLE 1754 def_bool y 1755 depends on HIBERNATION || KEXEC_CORE 1756 1757config XEN_DOM0 1758 def_bool y 1759 depends on XEN 1760 1761config XEN 1762 bool "Xen guest support on ARM64" 1763 depends on ARM64 && OF 1764 select SWIOTLB_XEN 1765 select PARAVIRT 1766 help 1767 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1768 1769# include/linux/mmzone.h requires the following to be true: 1770# 1771# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1772# 1773# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1774# 1775# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1776# ----+-------------------+--------------+----------------------+-------------------------+ 1777# 4K | 27 | 12 | 15 | 10 | 1778# 16K | 27 | 14 | 13 | 11 | 1779# 64K | 29 | 16 | 13 | 13 | 1780config ARCH_FORCE_MAX_ORDER 1781 int 1782 default "13" if ARM64_64K_PAGES 1783 default "11" if ARM64_16K_PAGES 1784 default "10" 1785 help 1786 The kernel page allocator limits the size of maximal physically 1787 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1788 defines the maximal power of two of number of pages that can be 1789 allocated as a single contiguous block. This option allows 1790 overriding the default setting when ability to allocate very 1791 large blocks of physically contiguous memory is required. 1792 1793 The maximal size of allocation cannot exceed the size of the 1794 section, so the value of MAX_PAGE_ORDER should satisfy 1795 1796 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1797 1798 Don't change if unsure. 1799 1800config UNMAP_KERNEL_AT_EL0 1801 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1802 default y 1803 help 1804 Speculation attacks against some high-performance processors can 1805 be used to bypass MMU permission checks and leak kernel data to 1806 userspace. This can be defended against by unmapping the kernel 1807 when running in userspace, mapping it back in on exception entry 1808 via a trampoline page in the vector table. 1809 1810 If unsure, say Y. 1811 1812config MITIGATE_SPECTRE_BRANCH_HISTORY 1813 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1814 default y 1815 help 1816 Speculation attacks against some high-performance processors can 1817 make use of branch history to influence future speculation. 1818 When taking an exception from user-space, a sequence of branches 1819 or a firmware call overwrites the branch history. 1820 1821config ARM64_SW_TTBR0_PAN 1822 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1823 depends on !KCSAN 1824 help 1825 Enabling this option prevents the kernel from accessing 1826 user-space memory directly by pointing TTBR0_EL1 to a reserved 1827 zeroed area and reserved ASID. The user access routines 1828 restore the valid TTBR0_EL1 temporarily. 1829 1830config ARM64_TAGGED_ADDR_ABI 1831 bool "Enable the tagged user addresses syscall ABI" 1832 default y 1833 help 1834 When this option is enabled, user applications can opt in to a 1835 relaxed ABI via prctl() allowing tagged addresses to be passed 1836 to system calls as pointer arguments. For details, see 1837 Documentation/arch/arm64/tagged-address-abi.rst. 1838 1839menuconfig COMPAT 1840 bool "Kernel support for 32-bit EL0" 1841 depends on ARM64_4K_PAGES || EXPERT 1842 select HAVE_UID16 1843 select OLD_SIGSUSPEND3 1844 select COMPAT_OLD_SIGACTION 1845 help 1846 This option enables support for a 32-bit EL0 running under a 64-bit 1847 kernel at EL1. AArch32-specific components such as system calls, 1848 the user helper functions, VFP support and the ptrace interface are 1849 handled appropriately by the kernel. 1850 1851 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1852 that you will only be able to execute AArch32 binaries that were compiled 1853 with page size aligned segments. 1854 1855 If you want to execute 32-bit userspace applications, say Y. 1856 1857if COMPAT 1858 1859config KUSER_HELPERS 1860 bool "Enable kuser helpers page for 32-bit applications" 1861 default y 1862 help 1863 Warning: disabling this option may break 32-bit user programs. 1864 1865 Provide kuser helpers to compat tasks. The kernel provides 1866 helper code to userspace in read only form at a fixed location 1867 to allow userspace to be independent of the CPU type fitted to 1868 the system. This permits binaries to be run on ARMv4 through 1869 to ARMv8 without modification. 1870 1871 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1872 1873 However, the fixed address nature of these helpers can be used 1874 by ROP (return orientated programming) authors when creating 1875 exploits. 1876 1877 If all of the binaries and libraries which run on your platform 1878 are built specifically for your platform, and make no use of 1879 these helpers, then you can turn this option off to hinder 1880 such exploits. However, in that case, if a binary or library 1881 relying on those helpers is run, it will not function correctly. 1882 1883 Say N here only if you are absolutely certain that you do not 1884 need these helpers; otherwise, the safe option is to say Y. 1885 1886config COMPAT_VDSO 1887 bool "Enable vDSO for 32-bit applications" 1888 depends on !CPU_BIG_ENDIAN 1889 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1890 default y 1891 help 1892 Place in the process address space of 32-bit applications an 1893 ELF shared object providing fast implementations of gettimeofday 1894 and clock_gettime. 1895 1896 You must have a 32-bit build of glibc 2.22 or later for programs 1897 to seamlessly take advantage of this. 1898 1899config THUMB2_COMPAT_VDSO 1900 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1901 depends on COMPAT_VDSO 1902 default y 1903 help 1904 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1905 otherwise with '-marm'. 1906 1907config COMPAT_ALIGNMENT_FIXUPS 1908 bool "Fix up misaligned multi-word loads and stores in user space" 1909 1910menuconfig ARMV8_DEPRECATED 1911 bool "Emulate deprecated/obsolete ARMv8 instructions" 1912 depends on SYSCTL 1913 help 1914 Legacy software support may require certain instructions 1915 that have been deprecated or obsoleted in the architecture. 1916 1917 Enable this config to enable selective emulation of these 1918 features. 1919 1920 If unsure, say Y 1921 1922if ARMV8_DEPRECATED 1923 1924config SWP_EMULATION 1925 bool "Emulate SWP/SWPB instructions" 1926 help 1927 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1928 they are always undefined. Say Y here to enable software 1929 emulation of these instructions for userspace using LDXR/STXR. 1930 This feature can be controlled at runtime with the abi.swp 1931 sysctl which is disabled by default. 1932 1933 In some older versions of glibc [<=2.8] SWP is used during futex 1934 trylock() operations with the assumption that the code will not 1935 be preempted. This invalid assumption may be more likely to fail 1936 with SWP emulation enabled, leading to deadlock of the user 1937 application. 1938 1939 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1940 on an external transaction monitoring block called a global 1941 monitor to maintain update atomicity. If your system does not 1942 implement a global monitor, this option can cause programs that 1943 perform SWP operations to uncached memory to deadlock. 1944 1945 If unsure, say Y 1946 1947config CP15_BARRIER_EMULATION 1948 bool "Emulate CP15 Barrier instructions" 1949 help 1950 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1951 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1952 strongly recommended to use the ISB, DSB, and DMB 1953 instructions instead. 1954 1955 Say Y here to enable software emulation of these 1956 instructions for AArch32 userspace code. When this option is 1957 enabled, CP15 barrier usage is traced which can help 1958 identify software that needs updating. This feature can be 1959 controlled at runtime with the abi.cp15_barrier sysctl. 1960 1961 If unsure, say Y 1962 1963config SETEND_EMULATION 1964 bool "Emulate SETEND instruction" 1965 help 1966 The SETEND instruction alters the data-endianness of the 1967 AArch32 EL0, and is deprecated in ARMv8. 1968 1969 Say Y here to enable software emulation of the instruction 1970 for AArch32 userspace code. This feature can be controlled 1971 at runtime with the abi.setend sysctl. 1972 1973 Note: All the cpus on the system must have mixed endian support at EL0 1974 for this feature to be enabled. If a new CPU - which doesn't support mixed 1975 endian - is hotplugged in after this feature has been enabled, there could 1976 be unexpected results in the applications. 1977 1978 If unsure, say Y 1979endif # ARMV8_DEPRECATED 1980 1981endif # COMPAT 1982 1983menu "ARMv8.1 architectural features" 1984 1985config ARM64_HW_AFDBM 1986 bool "Support for hardware updates of the Access and Dirty page flags" 1987 default y 1988 help 1989 The ARMv8.1 architecture extensions introduce support for 1990 hardware updates of the access and dirty information in page 1991 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1992 capable processors, accesses to pages with PTE_AF cleared will 1993 set this bit instead of raising an access flag fault. 1994 Similarly, writes to read-only pages with the DBM bit set will 1995 clear the read-only bit (AP[2]) instead of raising a 1996 permission fault. 1997 1998 Kernels built with this configuration option enabled continue 1999 to work on pre-ARMv8.1 hardware and the performance impact is 2000 minimal. If unsure, say Y. 2001 2002endmenu # "ARMv8.1 architectural features" 2003 2004menu "ARMv8.2 architectural features" 2005 2006config ARM64_PMEM 2007 bool "Enable support for persistent memory" 2008 select ARCH_HAS_PMEM_API 2009 select ARCH_HAS_UACCESS_FLUSHCACHE 2010 help 2011 Say Y to enable support for the persistent memory API based on the 2012 ARMv8.2 DCPoP feature. 2013 2014 The feature is detected at runtime, and the kernel will use DC CVAC 2015 operations if DC CVAP is not supported (following the behaviour of 2016 DC CVAP itself if the system does not define a point of persistence). 2017 2018config ARM64_RAS_EXTN 2019 bool "Enable support for RAS CPU Extensions" 2020 default y 2021 help 2022 CPUs that support the Reliability, Availability and Serviceability 2023 (RAS) Extensions, part of ARMv8.2 are able to track faults and 2024 errors, classify them and report them to software. 2025 2026 On CPUs with these extensions system software can use additional 2027 barriers to determine if faults are pending and read the 2028 classification from a new set of registers. 2029 2030 Selecting this feature will allow the kernel to use these barriers 2031 and access the new registers if the system supports the extension. 2032 Platform RAS features may additionally depend on firmware support. 2033 2034config ARM64_CNP 2035 bool "Enable support for Common Not Private (CNP) translations" 2036 default y 2037 help 2038 Common Not Private (CNP) allows translation table entries to 2039 be shared between different PEs in the same inner shareable 2040 domain, so the hardware can use this fact to optimise the 2041 caching of such entries in the TLB. 2042 2043 Selecting this option allows the CNP feature to be detected 2044 at runtime, and does not affect PEs that do not implement 2045 this feature. 2046 2047endmenu # "ARMv8.2 architectural features" 2048 2049menu "ARMv8.3 architectural features" 2050 2051config ARM64_PTR_AUTH 2052 bool "Enable support for pointer authentication" 2053 default y 2054 help 2055 Pointer authentication (part of the ARMv8.3 Extensions) provides 2056 instructions for signing and authenticating pointers against secret 2057 keys, which can be used to mitigate Return Oriented Programming (ROP) 2058 and other attacks. 2059 2060 This option enables these instructions at EL0 (i.e. for userspace). 2061 Choosing this option will cause the kernel to initialise secret keys 2062 for each process at exec() time, with these keys being 2063 context-switched along with the process. 2064 2065 The feature is detected at runtime. If the feature is not present in 2066 hardware it will not be advertised to userspace/KVM guest nor will it 2067 be enabled. 2068 2069 If the feature is present on the boot CPU but not on a late CPU, then 2070 the late CPU will be parked. Also, if the boot CPU does not have 2071 address auth and the late CPU has then the late CPU will still boot 2072 but with the feature disabled. On such a system, this option should 2073 not be selected. 2074 2075config ARM64_PTR_AUTH_KERNEL 2076 bool "Use pointer authentication for kernel" 2077 default y 2078 depends on ARM64_PTR_AUTH 2079 # Modern compilers insert a .note.gnu.property section note for PAC 2080 # which is only understood by binutils starting with version 2.33.1. 2081 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 2082 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 2083 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2084 help 2085 If the compiler supports the -mbranch-protection or 2086 -msign-return-address flag (e.g. GCC 7 or later), then this option 2087 will cause the kernel itself to be compiled with return address 2088 protection. In this case, and if the target hardware is known to 2089 support pointer authentication, then CONFIG_STACKPROTECTOR can be 2090 disabled with minimal loss of protection. 2091 2092 This feature works with FUNCTION_GRAPH_TRACER option only if 2093 DYNAMIC_FTRACE_WITH_ARGS is enabled. 2094 2095config CC_HAS_BRANCH_PROT_PAC_RET 2096 # GCC 9 or later, clang 8 or later 2097 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 2098 2099config AS_HAS_CFI_NEGATE_RA_STATE 2100 # binutils 2.34+ 2101 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2102 2103endmenu # "ARMv8.3 architectural features" 2104 2105menu "ARMv8.4 architectural features" 2106 2107config ARM64_AMU_EXTN 2108 bool "Enable support for the Activity Monitors Unit CPU extension" 2109 default y 2110 help 2111 The activity monitors extension is an optional extension introduced 2112 by the ARMv8.4 CPU architecture. This enables support for version 1 2113 of the activity monitors architecture, AMUv1. 2114 2115 To enable the use of this extension on CPUs that implement it, say Y. 2116 2117 Note that for architectural reasons, firmware _must_ implement AMU 2118 support when running on CPUs that present the activity monitors 2119 extension. The required support is present in: 2120 * Version 1.5 and later of the ARM Trusted Firmware 2121 2122 For kernels that have this configuration enabled but boot with broken 2123 firmware, you may need to say N here until the firmware is fixed. 2124 Otherwise you may experience firmware panics or lockups when 2125 accessing the counter registers. Even if you are not observing these 2126 symptoms, the values returned by the register reads might not 2127 correctly reflect reality. Most commonly, the value read will be 0, 2128 indicating that the counter is not enabled. 2129 2130config ARM64_TLB_RANGE 2131 bool "Enable support for tlbi range feature" 2132 default y 2133 help 2134 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2135 range of input addresses. 2136 2137config ARM64_MPAM 2138 bool "Enable support for MPAM" 2139 select ARM64_MPAM_DRIVER 2140 select ARCH_HAS_CPU_RESCTRL 2141 help 2142 Memory System Resource Partitioning and Monitoring (MPAM) is an 2143 optional extension to the Arm architecture that allows each 2144 transaction issued to the memory system to be labelled with a 2145 Partition identifier (PARTID) and Performance Monitoring Group 2146 identifier (PMG). 2147 2148 Memory system components, such as the caches, can be configured with 2149 policies to control how much of various physical resources (such as 2150 memory bandwidth or cache memory) the transactions labelled with each 2151 PARTID can consume. Depending on the capabilities of the hardware, 2152 the PARTID and PMG can also be used as filtering criteria to measure 2153 the memory system resource consumption of different parts of a 2154 workload. 2155 2156 Use of this extension requires CPU support, support in the 2157 Memory System Components (MSC), and a description from firmware 2158 of where the MSCs are in the address space. 2159 2160 MPAM is exposed to user-space via the resctrl pseudo filesystem. 2161 2162 This option enables the extra context switch code. 2163 2164endmenu # "ARMv8.4 architectural features" 2165 2166menu "ARMv8.5 architectural features" 2167 2168config AS_HAS_ARMV8_5 2169 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2170 2171config ARM64_BTI 2172 bool "Branch Target Identification support" 2173 default y 2174 help 2175 Branch Target Identification (part of the ARMv8.5 Extensions) 2176 provides a mechanism to limit the set of locations to which computed 2177 branch instructions such as BR or BLR can jump. 2178 2179 To make use of BTI on CPUs that support it, say Y. 2180 2181 BTI is intended to provide complementary protection to other control 2182 flow integrity protection mechanisms, such as the Pointer 2183 authentication mechanism provided as part of the ARMv8.3 Extensions. 2184 For this reason, it does not make sense to enable this option without 2185 also enabling support for pointer authentication. Thus, when 2186 enabling this option you should also select ARM64_PTR_AUTH=y. 2187 2188 Userspace binaries must also be specifically compiled to make use of 2189 this mechanism. If you say N here or the hardware does not support 2190 BTI, such binaries can still run, but you get no additional 2191 enforcement of branch destinations. 2192 2193config ARM64_BTI_KERNEL 2194 bool "Use Branch Target Identification for kernel" 2195 default y 2196 depends on ARM64_BTI 2197 depends on ARM64_PTR_AUTH_KERNEL 2198 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2199 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2200 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2201 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2202 depends on !CC_IS_GCC 2203 # https://github.com/llvm/llvm-project/issues/215547 2204 depends on !CC_IS_CLANG || CLANG_VERSION < 210000 2205 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2206 help 2207 Build the kernel with Branch Target Identification annotations 2208 and enable enforcement of this for kernel code. When this option 2209 is enabled and the system supports BTI all kernel code including 2210 modular code must have BTI enabled. 2211 2212config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2213 # GCC 9 or later, clang 8 or later 2214 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2215 2216config ARM64_E0PD 2217 bool "Enable support for E0PD" 2218 default y 2219 help 2220 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2221 that EL0 accesses made via TTBR1 always fault in constant time, 2222 providing similar benefits to KASLR as those provided by KPTI, but 2223 with lower overhead and without disrupting legitimate access to 2224 kernel memory such as SPE. 2225 2226 This option enables E0PD for TTBR1 where available. 2227 2228config ARM64_AS_HAS_MTE 2229 # Initial support for MTE went in binutils 2.32.0, checked with 2230 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2231 # as a late addition to the final architecture spec (LDGM/STGM) 2232 # is only supported in the newer 2.32.x and 2.33 binutils 2233 # versions, hence the extra "stgm" instruction check below. 2234 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2235 2236config ARM64_MTE 2237 bool "Memory Tagging Extension support" 2238 default y 2239 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2240 depends on AS_HAS_ARMV8_5 2241 # Required for tag checking in the uaccess routines 2242 select ARCH_HAS_SUBPAGE_FAULTS 2243 select ARCH_USES_HIGH_VMA_FLAGS 2244 select ARCH_USES_PG_ARCH_2 2245 select ARCH_USES_PG_ARCH_3 2246 help 2247 Memory Tagging (part of the ARMv8.5 Extensions) provides 2248 architectural support for run-time, always-on detection of 2249 various classes of memory error to aid with software debugging 2250 to eliminate vulnerabilities arising from memory-unsafe 2251 languages. 2252 2253 This option enables the support for the Memory Tagging 2254 Extension at EL0 (i.e. for userspace). 2255 2256 Selecting this option allows the feature to be detected at 2257 runtime. Any secondary CPU not implementing this feature will 2258 not be allowed a late bring-up. 2259 2260 Userspace binaries that want to use this feature must 2261 explicitly opt in. The mechanism for the userspace is 2262 described in: 2263 2264 Documentation/arch/arm64/memory-tagging-extension.rst. 2265 2266endmenu # "ARMv8.5 architectural features" 2267 2268menu "ARMv8.7 architectural features" 2269 2270config ARM64_EPAN 2271 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2272 default y 2273 help 2274 Enhanced Privileged Access Never (EPAN) allows Privileged 2275 Access Never to be used with Execute-only mappings. 2276 2277 The feature is detected at runtime, and will remain disabled 2278 if the cpu does not implement the feature. 2279endmenu # "ARMv8.7 architectural features" 2280 2281config AS_HAS_MOPS 2282 def_bool $(as-instr,.arch_extension mops) 2283 2284menu "ARMv8.9 architectural features" 2285 2286config ARM64_POE 2287 prompt "Permission Overlay Extension" 2288 def_bool y 2289 select ARCH_USES_HIGH_VMA_FLAGS 2290 select ARCH_HAS_PKEYS 2291 help 2292 The Permission Overlay Extension is used to implement Memory 2293 Protection Keys. Memory Protection Keys provides a mechanism for 2294 enforcing page-based protections, but without requiring modification 2295 of the page tables when an application changes protection domains. 2296 2297 For details, see Documentation/core-api/protection-keys.rst 2298 2299 If unsure, say y. 2300 2301config ARCH_PKEY_BITS 2302 int 2303 default 3 2304 2305config ARM64_HAFT 2306 bool "Support for Hardware managed Access Flag for Table Descriptors" 2307 depends on ARM64_HW_AFDBM 2308 default y 2309 help 2310 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2311 Flag for Table descriptors. When enabled an architectural executed 2312 memory access will update the Access Flag in each Table descriptor 2313 which is accessed during the translation table walk and for which 2314 the Access Flag is 0. The Access Flag of the Table descriptor use 2315 the same bit of PTE_AF. 2316 2317 The feature will only be enabled if all the CPUs in the system 2318 support this feature. If unsure, say Y. 2319 2320endmenu # "ARMv8.9 architectural features" 2321 2322menu "ARMv9.4 architectural features" 2323 2324config ARM64_GCS 2325 bool "Enable support for Guarded Control Stack (GCS)" 2326 default y 2327 select ARCH_HAS_USER_SHADOW_STACK 2328 select ARCH_USES_HIGH_VMA_FLAGS 2329 help 2330 Guarded Control Stack (GCS) provides support for a separate 2331 stack with restricted access which contains only return 2332 addresses. This can be used to harden against some attacks 2333 by comparing return address used by the program with what is 2334 stored in the GCS, and may also be used to efficiently obtain 2335 the call stack for applications such as profiling. 2336 2337 The feature is detected at runtime, and will remain disabled 2338 if the system does not implement the feature. 2339 2340endmenu # "ARMv9.4 architectural features" 2341 2342config AS_HAS_LSUI 2343 def_bool $(as-instr,.arch_extension lsui) 2344 help 2345 Supported by LLVM 20+ and binutils 2.45+. 2346 2347menu "ARMv9.6 architectural features" 2348 2349config ARM64_LSUI 2350 bool "Support Unprivileged Load Store Instructions (LSUI)" 2351 default y 2352 depends on AS_HAS_LSUI && !CPU_BIG_ENDIAN 2353 help 2354 The Unprivileged Load Store Instructions (LSUI) provides 2355 variants load/store instructions that access user-space memory 2356 from the kernel without clearing PSTATE.PAN bit. 2357 2358 This feature is supported by LLVM 20+ and binutils 2.45+. 2359 2360endmenu # "ARMv9.6 architectural feature" 2361 2362config ARM64_SVE 2363 bool "ARM Scalable Vector Extension support" 2364 default y 2365 help 2366 The Scalable Vector Extension (SVE) is an extension to the AArch64 2367 execution state which complements and extends the SIMD functionality 2368 of the base architecture to support much larger vectors and to enable 2369 additional vectorisation opportunities. 2370 2371 To enable use of this extension on CPUs that implement it, say Y. 2372 2373 On CPUs that support the SVE2 extensions, this option will enable 2374 those too. 2375 2376 Note that for architectural reasons, firmware _must_ implement SVE 2377 support when running on SVE capable hardware. The required support 2378 is present in: 2379 2380 * version 1.5 and later of the ARM Trusted Firmware 2381 * the AArch64 boot wrapper since commit 5e1261e08abf 2382 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2383 2384 For other firmware implementations, consult the firmware documentation 2385 or vendor. 2386 2387 If you need the kernel to boot on SVE-capable hardware with broken 2388 firmware, you may need to say N here until you get your firmware 2389 fixed. Otherwise, you may experience firmware panics or lockups when 2390 booting the kernel. If unsure and you are not observing these 2391 symptoms, you should assume that it is safe to say Y. 2392 2393config AS_HAS_SME 2394 # Supported by LLVM 13+ and binutils 2.38+ 2395 def_bool $(as-instr,.arch_extension sme) 2396 2397config ARM64_SME 2398 bool "ARM Scalable Matrix Extension support" 2399 default y 2400 depends on ARM64_SVE 2401 depends on AS_HAS_SME 2402 help 2403 The Scalable Matrix Extension (SME) is an extension to the AArch64 2404 execution state which utilises a substantial subset of the SVE 2405 instruction set, together with the addition of new architectural 2406 register state capable of holding two dimensional matrix tiles to 2407 enable various matrix operations. 2408 2409config ARM64_PSEUDO_NMI 2410 bool "Support for NMI-like interrupts" 2411 select ARM_GIC_V3 2412 help 2413 Adds support for mimicking Non-Maskable Interrupts through the use of 2414 GIC interrupt priority. This support requires version 3 or later of 2415 ARM GIC. 2416 2417 This high priority configuration for interrupts needs to be 2418 explicitly enabled by setting the kernel parameter 2419 "irqchip.gicv3_pseudo_nmi" to 1. 2420 2421 If unsure, say N 2422 2423if ARM64_PSEUDO_NMI 2424config ARM64_DEBUG_PRIORITY_MASKING 2425 bool "Debug interrupt priority masking" 2426 help 2427 This adds runtime checks to functions enabling/disabling 2428 interrupts when using priority masking. The additional checks verify 2429 the validity of ICC_PMR_EL1 when calling concerned functions. 2430 2431 If unsure, say N 2432endif # ARM64_PSEUDO_NMI 2433 2434config RELOCATABLE 2435 bool "Build a relocatable kernel image" if EXPERT 2436 select ARCH_HAS_RELR 2437 default y 2438 help 2439 This builds the kernel as a Position Independent Executable (PIE), 2440 which retains all relocation metadata required to relocate the 2441 kernel binary at runtime to a different virtual address than the 2442 address it was linked at. 2443 Since AArch64 uses the RELA relocation format, this requires a 2444 relocation pass at runtime even if the kernel is loaded at the 2445 same address it was linked at. 2446 2447config RANDOMIZE_BASE 2448 bool "Randomize the address of the kernel image" 2449 select RELOCATABLE 2450 help 2451 Randomizes the virtual address at which the kernel image is 2452 loaded, as a security feature that deters exploit attempts 2453 relying on knowledge of the location of kernel internals. 2454 2455 It is the bootloader's job to provide entropy, by passing a 2456 random u64 value in /chosen/kaslr-seed at kernel entry. 2457 2458 When booting via the UEFI stub, it will invoke the firmware's 2459 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2460 to the kernel proper. In addition, it will randomise the physical 2461 location of the kernel Image as well. 2462 2463 If unsure, say N. 2464 2465config RANDOMIZE_MODULE_REGION_FULL 2466 bool "Randomize the module region over a 2 GB range" 2467 depends on RANDOMIZE_BASE 2468 default y 2469 help 2470 Randomizes the location of the module region inside a 2 GB window 2471 covering the core kernel. This way, it is less likely for modules 2472 to leak information about the location of core kernel data structures 2473 but it does imply that function calls between modules and the core 2474 kernel will need to be resolved via veneers in the module PLT. 2475 2476 When this option is not set, the module region will be randomized over 2477 a limited range that contains the [_stext, _etext] interval of the 2478 core kernel, so branch relocations are almost always in range unless 2479 the region is exhausted. In this particular case of region 2480 exhaustion, modules might be able to fall back to a larger 2GB area. 2481 2482config CC_HAVE_STACKPROTECTOR_SYSREG 2483 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2484 2485config STACKPROTECTOR_PER_TASK 2486 def_bool y 2487 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2488 2489config UNWIND_PATCH_PAC_INTO_SCS 2490 bool "Enable shadow call stack dynamically using code patching" 2491 depends on CC_IS_CLANG 2492 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2493 depends on SHADOW_CALL_STACK 2494 select UNWIND_TABLES 2495 select DYNAMIC_SCS 2496 2497config ARM64_CONTPTE 2498 bool "Contiguous PTE mappings for user memory" if EXPERT 2499 depends on TRANSPARENT_HUGEPAGE 2500 default y 2501 help 2502 When enabled, user mappings are configured using the PTE contiguous 2503 bit, for any mappings that meet the size and alignment requirements. 2504 This reduces TLB pressure and improves performance. 2505 2506endmenu # "Kernel Features" 2507 2508menu "Boot options" 2509 2510config ARM64_ACPI_PARKING_PROTOCOL 2511 bool "Enable support for the ARM64 ACPI parking protocol" 2512 depends on ACPI 2513 help 2514 Enable support for the ARM64 ACPI parking protocol. If disabled 2515 the kernel will not allow booting through the ARM64 ACPI parking 2516 protocol even if the corresponding data is present in the ACPI 2517 MADT table. 2518 2519config CMDLINE 2520 string "Default kernel command string" 2521 default "" 2522 help 2523 Provide a set of default command-line options at build time by 2524 entering them here. As a minimum, you should specify the 2525 root device (e.g. root=/dev/nfs). 2526 2527choice 2528 prompt "Kernel command line type" 2529 depends on CMDLINE != "" 2530 default CMDLINE_FROM_BOOTLOADER 2531 help 2532 Choose how the kernel will handle the provided default kernel 2533 command line string. 2534 2535config CMDLINE_FROM_BOOTLOADER 2536 bool "Use bootloader kernel arguments if available" 2537 help 2538 Uses the command-line options passed by the boot loader. If 2539 the boot loader doesn't provide any, the default kernel command 2540 string provided in CMDLINE will be used. 2541 2542config CMDLINE_FORCE 2543 bool "Always use the default kernel command string" 2544 help 2545 Always use the default kernel command string, even if the boot 2546 loader passes other arguments to the kernel. 2547 This is useful if you cannot or don't want to change the 2548 command-line options your boot loader passes to the kernel. 2549 2550endchoice 2551 2552config EFI_STUB 2553 bool 2554 2555config EFI 2556 bool "UEFI runtime support" 2557 depends on OF && !CPU_BIG_ENDIAN 2558 depends on KERNEL_MODE_NEON 2559 select ARCH_SUPPORTS_ACPI 2560 select LIBFDT 2561 select UCS2_STRING 2562 select EFI_PARAMS_FROM_FDT 2563 select EFI_RUNTIME_WRAPPERS 2564 select EFI_STUB 2565 select EFI_GENERIC_STUB 2566 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2567 default y 2568 help 2569 This option provides support for runtime services provided 2570 by UEFI firmware (such as non-volatile variables, realtime 2571 clock, and platform reset). A UEFI stub is also provided to 2572 allow the kernel to be booted as an EFI application. This 2573 is only useful on systems that have UEFI firmware. 2574 2575config COMPRESSED_INSTALL 2576 bool "Install compressed image by default" 2577 help 2578 This makes the regular "make install" install the compressed 2579 image we built, not the legacy uncompressed one. 2580 2581 You can check that a compressed image works for you by doing 2582 "make zinstall" first, and verifying that everything is fine 2583 in your environment before making "make install" do this for 2584 you. 2585 2586config DMI 2587 bool "Enable support for SMBIOS (DMI) tables" 2588 depends on EFI 2589 default y 2590 help 2591 This enables SMBIOS/DMI feature for systems. 2592 2593 This option is only useful on systems that have UEFI firmware. 2594 However, even with this option, the resultant kernel should 2595 continue to boot on existing non-UEFI platforms. 2596 2597endmenu # "Boot options" 2598 2599menu "Power management options" 2600 2601source "kernel/power/Kconfig" 2602 2603config ARCH_HIBERNATION_POSSIBLE 2604 def_bool y 2605 depends on CPU_PM 2606 2607config ARCH_HIBERNATION_HEADER 2608 def_bool y 2609 depends on HIBERNATION 2610 2611config ARCH_SUSPEND_POSSIBLE 2612 def_bool y 2613 2614endmenu # "Power management options" 2615 2616menu "CPU Power Management" 2617 2618source "drivers/cpuidle/Kconfig" 2619 2620source "drivers/cpufreq/Kconfig" 2621 2622endmenu # "CPU Power Management" 2623 2624source "drivers/acpi/Kconfig" 2625 2626source "arch/arm64/kvm/Kconfig" 2627 2628source "kernel/livepatch/Kconfig" 2629