1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_MEMBARRIER_SYNC_CORE 38 select ARCH_HAS_MEM_ENCRYPT 39 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS 40 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 41 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 42 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 43 select ARCH_HAS_PREEMPT_LAZY 44 select ARCH_HAS_PTDUMP 45 select ARCH_HAS_PTE_SPECIAL 46 select ARCH_HAS_HW_PTE_YOUNG 47 select ARCH_HAS_SETUP_DMA_OPS 48 select ARCH_HAS_SET_DIRECT_MAP 49 select ARCH_HAS_SET_MEMORY 50 select ARCH_HAS_MEM_ENCRYPT 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_SYSCALL_WRAPPER 58 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 59 select ARCH_HAS_ZONE_DMA_SET if EXPERT 60 select ARCH_HAVE_ELF_PROT 61 select ARCH_HAVE_NMI_SAFE_CMPXCHG 62 select ARCH_HAVE_TRACE_MMIO_ACCESS 63 select ARCH_INLINE_READ_LOCK if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 65 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 70 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 73 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 74 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 77 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 78 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 79 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 83 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 84 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 87 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 88 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 89 select ARCH_KEEP_MEMBLOCK 90 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 91 select ARCH_USE_CMPXCHG_LOCKREF 92 select ARCH_USE_GNU_PROPERTY 93 select ARCH_USE_MEMTEST 94 select ARCH_USE_QUEUED_RWLOCKS 95 select ARCH_USE_QUEUED_SPINLOCKS 96 select ARCH_USE_SYM_ANNOTATIONS 97 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 98 select ARCH_SUPPORTS_HUGETLBFS 99 select ARCH_SUPPORTS_MEMORY_FAILURE 100 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 101 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 102 select ARCH_SUPPORTS_LTO_CLANG_THIN 103 select ARCH_SUPPORTS_CFI 104 select ARCH_SUPPORTS_ATOMIC_RMW 105 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 106 select ARCH_SUPPORTS_NUMA_BALANCING 107 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 108 select ARCH_SUPPORTS_PER_VMA_LOCK 109 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 110 select ARCH_SUPPORTS_RT 111 select ARCH_SUPPORTS_SCHED_SMT 112 select ARCH_SUPPORTS_SCHED_CLUSTER 113 select ARCH_SUPPORTS_SCHED_MC 114 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 115 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 116 select ARCH_WANT_DEFAULT_BPF_JIT 117 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 118 select ARCH_WANT_FRAME_POINTERS 119 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 120 select ARCH_WANT_LD_ORPHAN_WARN 121 select ARCH_WANTS_EXECMEM_LATE 122 select ARCH_WANTS_NO_INSTR 123 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 124 select ARCH_HAS_UBSAN 125 select ARM_AMBA 126 select ARM_ARCH_TIMER 127 select ARM_GIC 128 select AUDIT_ARCH_COMPAT_GENERIC 129 select ARM_GIC_V2M if PCI 130 select ARM_GIC_V3 131 select ARM_GIC_V3_ITS if PCI 132 select ARM_GIC_V5 133 select ARM_PSCI_FW 134 select BUILDTIME_TABLE_SORT 135 select CLONE_BACKWARDS 136 select COMMON_CLK 137 select CPU_PM if (SUSPEND || CPU_IDLE) 138 select CPUMASK_OFFSTACK if NR_CPUS > 256 139 select DCACHE_WORD_ACCESS 140 select HAVE_EXTRA_IPI_TRACEPOINTS 141 select DYNAMIC_FTRACE if FUNCTION_TRACER 142 select DMA_BOUNCE_UNALIGNED_KMALLOC 143 select DMA_DIRECT_REMAP 144 select EDAC_SUPPORT 145 select FRAME_POINTER 146 select FUNCTION_ALIGNMENT_4B 147 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 148 select GENERIC_ALLOCATOR 149 select GENERIC_ARCH_TOPOLOGY 150 select GENERIC_CLOCKEVENTS_BROADCAST 151 select GENERIC_CPU_AUTOPROBE 152 select GENERIC_CPU_DEVICES 153 select GENERIC_CPU_VULNERABILITIES 154 select GENERIC_EARLY_IOREMAP 155 select GENERIC_IDLE_POLL_SETUP 156 select GENERIC_IOREMAP 157 select GENERIC_IRQ_ENTRY 158 select GENERIC_IRQ_IPI 159 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 160 select GENERIC_IRQ_PROBE 161 select GENERIC_IRQ_SHOW 162 select GENERIC_IRQ_SHOW_LEVEL 163 select GENERIC_LIB_DEVMEM_IS_ALLOWED 164 select GENERIC_PCI_IOMAP 165 select GENERIC_SCHED_CLOCK 166 select GENERIC_SMP_IDLE_THREAD 167 select GENERIC_TIME_VSYSCALL 168 select GENERIC_GETTIMEOFDAY 169 select HARDIRQS_SW_RESEND 170 select HAS_IOPORT 171 select HAVE_MOVE_PMD 172 select HAVE_MOVE_PUD 173 select HAVE_PCI 174 select HAVE_ACPI_APEI if (ACPI && EFI) 175 select HAVE_ALIGNED_STRUCT_PAGE 176 select HAVE_ARCH_AUDITSYSCALL 177 select HAVE_ARCH_BITREVERSE 178 select HAVE_ARCH_COMPILER_H 179 select HAVE_ARCH_HUGE_VMALLOC 180 select HAVE_ARCH_HUGE_VMAP 181 select HAVE_ARCH_JUMP_LABEL 182 select HAVE_ARCH_JUMP_LABEL_RELATIVE 183 select HAVE_ARCH_KASAN 184 select HAVE_ARCH_KASAN_VMALLOC 185 select HAVE_ARCH_KASAN_SW_TAGS 186 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 187 # Some instrumentation may be unsound, hence EXPERT 188 select HAVE_ARCH_KCSAN if EXPERT 189 select HAVE_ARCH_KFENCE 190 select HAVE_ARCH_KGDB 191 select HAVE_ARCH_KSTACK_ERASE 192 select HAVE_ARCH_MMAP_RND_BITS 193 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 194 select HAVE_ARCH_PREL32_RELOCATIONS 195 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 196 select HAVE_ARCH_SECCOMP_FILTER 197 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 198 select HAVE_ARCH_TRACEHOOK 199 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 200 select HAVE_ARCH_VMAP_STACK 201 select HAVE_ARM_SMCCC 202 select HAVE_ASM_MODVERSIONS 203 select HAVE_EBPF_JIT 204 select HAVE_C_RECORDMCOUNT 205 select HAVE_CMPXCHG_DOUBLE 206 select HAVE_CMPXCHG_LOCAL 207 select HAVE_CONTEXT_TRACKING_USER 208 select HAVE_DEBUG_KMEMLEAK 209 select HAVE_DMA_CONTIGUOUS 210 select HAVE_DYNAMIC_FTRACE 211 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 212 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 213 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 214 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 215 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 216 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 217 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI && \ 218 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 219 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 220 if DYNAMIC_FTRACE_WITH_ARGS 221 select HAVE_SAMPLE_FTRACE_DIRECT 222 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 223 select HAVE_BUILDTIME_MCOUNT_SORT 224 select HAVE_EFFICIENT_UNALIGNED_ACCESS 225 select HAVE_GUP_FAST 226 select HAVE_FTRACE_GRAPH_FUNC 227 select HAVE_FUNCTION_TRACER 228 select HAVE_FUNCTION_ERROR_INJECTION 229 select HAVE_FUNCTION_GRAPH_FREGS 230 select HAVE_FUNCTION_GRAPH_TRACER 231 select HAVE_GCC_PLUGINS 232 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 233 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 234 select HAVE_HW_BREAKPOINT if PERF_EVENTS 235 select HAVE_IOREMAP_PROT 236 select HAVE_IRQ_TIME_ACCOUNTING 237 select HAVE_LIVEPATCH 238 select HAVE_MOD_ARCH_SPECIFIC 239 select HAVE_NMI 240 select HAVE_PERF_EVENTS 241 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 242 select HAVE_PERF_REGS 243 select HAVE_PERF_USER_STACK_DUMP 244 select HAVE_PREEMPT_DYNAMIC_KEY 245 select HAVE_REGS_AND_STACK_ACCESS_API 246 select HAVE_RELIABLE_STACKTRACE 247 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 248 select HAVE_FUNCTION_ARG_ACCESS_API 249 select MMU_GATHER_RCU_TABLE_FREE 250 select HAVE_RSEQ 251 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 252 select HAVE_STACKPROTECTOR 253 select HAVE_SYSCALL_TRACEPOINTS 254 select HAVE_KPROBES 255 select HAVE_KRETPROBES 256 select HAVE_GENERIC_VDSO 257 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 258 select HOTPLUG_SMT if HOTPLUG_CPU 259 select IRQ_DOMAIN 260 select IRQ_FORCED_THREADING 261 select JUMP_LABEL 262 select KASAN_VMALLOC if KASAN 263 select LOCK_MM_AND_FIND_VMA 264 select MODULES_USE_ELF_RELA 265 select NEED_DMA_MAP_STATE 266 select NEED_SG_DMA_LENGTH 267 select OF 268 select OF_EARLY_FLATTREE 269 select PCI_DOMAINS_GENERIC if PCI 270 select PCI_ECAM if (ACPI && PCI) 271 select PCI_SYSCALL if PCI 272 select POWER_RESET 273 select POWER_SUPPLY 274 select SPARSE_IRQ 275 select SWIOTLB 276 select SYSCTL_EXCEPTION_TRACE 277 select THREAD_INFO_IN_TASK 278 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 279 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 280 select TRACE_IRQFLAGS_SUPPORT 281 select TRACE_IRQFLAGS_NMI_SUPPORT 282 select HAVE_SOFTIRQ_ON_OWN_STACK 283 select USER_STACKTRACE_SUPPORT 284 select VDSO_GETRANDOM 285 select VMAP_STACK 286 help 287 ARM 64-bit (AArch64) Linux support. 288 289config RUSTC_SUPPORTS_ARM64 290 def_bool y 291 depends on CPU_LITTLE_ENDIAN 292 # Shadow call stack is only supported on certain rustc versions. 293 # 294 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 295 # required due to use of the -Zfixed-x18 flag. 296 # 297 # Otherwise, rustc version 1.82+ is required due to use of the 298 # -Zsanitizer=shadow-call-stack flag. 299 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 300 301config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 302 def_bool CC_IS_CLANG 303 # https://github.com/ClangBuiltLinux/linux/issues/1507 304 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 305 306config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 307 def_bool CC_IS_GCC 308 depends on $(cc-option,-fpatchable-function-entry=2) 309 310config 64BIT 311 def_bool y 312 313config MMU 314 def_bool y 315 316config ARM64_CONT_PTE_SHIFT 317 int 318 default 5 if PAGE_SIZE_64KB 319 default 7 if PAGE_SIZE_16KB 320 default 4 321 322config ARM64_CONT_PMD_SHIFT 323 int 324 default 5 if PAGE_SIZE_64KB 325 default 5 if PAGE_SIZE_16KB 326 default 4 327 328config ARCH_MMAP_RND_BITS_MIN 329 default 14 if PAGE_SIZE_64KB 330 default 16 if PAGE_SIZE_16KB 331 default 18 332 333# max bits determined by the following formula: 334# VA_BITS - PTDESC_TABLE_SHIFT 335config ARCH_MMAP_RND_BITS_MAX 336 default 19 if ARM64_VA_BITS=36 337 default 24 if ARM64_VA_BITS=39 338 default 27 if ARM64_VA_BITS=42 339 default 30 if ARM64_VA_BITS=47 340 default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES 341 default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES 342 default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) 343 default 14 if ARM64_64K_PAGES 344 default 16 if ARM64_16K_PAGES 345 default 18 346 347config ARCH_MMAP_RND_COMPAT_BITS_MIN 348 default 7 if ARM64_64K_PAGES 349 default 9 if ARM64_16K_PAGES 350 default 11 351 352config ARCH_MMAP_RND_COMPAT_BITS_MAX 353 default 16 354 355config NO_IOPORT_MAP 356 def_bool y if !PCI 357 358config STACKTRACE_SUPPORT 359 def_bool y 360 361config ILLEGAL_POINTER_VALUE 362 hex 363 default 0xdead000000000000 364 365config LOCKDEP_SUPPORT 366 def_bool y 367 368config GENERIC_BUG 369 def_bool y 370 depends on BUG 371 372config GENERIC_BUG_RELATIVE_POINTERS 373 def_bool y 374 depends on GENERIC_BUG 375 376config GENERIC_HWEIGHT 377 def_bool y 378 379config GENERIC_CSUM 380 def_bool y 381 382config GENERIC_CALIBRATE_DELAY 383 def_bool y 384 385config SMP 386 def_bool y 387 388config KERNEL_MODE_NEON 389 def_bool y 390 391config FIX_EARLYCON_MEM 392 def_bool y 393 394config PGTABLE_LEVELS 395 int 396 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 397 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 398 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 399 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 400 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 401 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 402 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 403 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 404 405config ARCH_SUPPORTS_UPROBES 406 def_bool y 407 408config ARCH_PROC_KCORE_TEXT 409 def_bool y 410 411config BROKEN_GAS_INST 412 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 413 414config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 415 bool 416 # Clang's __builtin_return_address() strips the PAC since 12.0.0 417 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 418 default y if CC_IS_CLANG 419 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 420 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 421 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 422 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 423 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 424 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 425 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 426 default n 427 428config KASAN_SHADOW_OFFSET 429 hex 430 depends on KASAN_GENERIC || KASAN_SW_TAGS 431 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 432 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 433 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 434 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 435 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 436 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 437 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 438 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 439 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 440 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 441 default 0xffffffffffffffff 442 443config UNWIND_TABLES 444 bool 445 446source "arch/arm64/Kconfig.platforms" 447 448menu "Kernel Features" 449 450menu "ARM errata workarounds via the alternatives framework" 451 452config AMPERE_ERRATUM_AC03_CPU_38 453 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 454 default y 455 help 456 This option adds an alternative code sequence to work around Ampere 457 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 458 459 The affected design reports FEAT_HAFDBS as not implemented in 460 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 461 as required by the architecture. The unadvertised HAFDBS 462 implementation suffers from an additional erratum where hardware 463 A/D updates can occur after a PTE has been marked invalid. 464 465 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 466 which avoids enabling unadvertised hardware Access Flag management 467 at stage-2. 468 469 If unsure, say Y. 470 471config AMPERE_ERRATUM_AC04_CPU_23 472 bool "AmpereOne: AC04_CPU_23: Failure to synchronize writes to HCR_EL2 may corrupt address translations." 473 default y 474 help 475 This option adds an alternative code sequence to work around Ampere 476 errata AC04_CPU_23 on AmpereOne. 477 478 Updates to HCR_EL2 can rarely corrupt simultaneous translations for 479 data addresses initiated by load/store instructions. Only 480 instruction initiated translations are vulnerable, not translations 481 from prefetches for example. A DSB before the store to HCR_EL2 is 482 sufficient to prevent older instructions from hitting the window 483 for corruption, and an ISB after is sufficient to prevent younger 484 instructions from hitting the window for corruption. 485 486 If unsure, say Y. 487 488config ARM64_WORKAROUND_CLEAN_CACHE 489 bool 490 491config ARM64_ERRATUM_826319 492 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 493 default y 494 select ARM64_WORKAROUND_CLEAN_CACHE 495 help 496 This option adds an alternative code sequence to work around ARM 497 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 498 AXI master interface and an L2 cache. 499 500 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 501 and is unable to accept a certain write via this interface, it will 502 not progress on read data presented on the read data channel and the 503 system can deadlock. 504 505 The workaround promotes data cache clean instructions to 506 data cache clean-and-invalidate. 507 Please note that this does not necessarily enable the workaround, 508 as it depends on the alternative framework, which will only patch 509 the kernel if an affected CPU is detected. 510 511 If unsure, say Y. 512 513config ARM64_ERRATUM_827319 514 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 515 default y 516 select ARM64_WORKAROUND_CLEAN_CACHE 517 help 518 This option adds an alternative code sequence to work around ARM 519 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 520 master interface and an L2 cache. 521 522 Under certain conditions this erratum can cause a clean line eviction 523 to occur at the same time as another transaction to the same address 524 on the AMBA 5 CHI interface, which can cause data corruption if the 525 interconnect reorders the two transactions. 526 527 The workaround promotes data cache clean instructions to 528 data cache clean-and-invalidate. 529 Please note that this does not necessarily enable the workaround, 530 as it depends on the alternative framework, which will only patch 531 the kernel if an affected CPU is detected. 532 533 If unsure, say Y. 534 535config ARM64_ERRATUM_824069 536 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 537 default y 538 select ARM64_WORKAROUND_CLEAN_CACHE 539 help 540 This option adds an alternative code sequence to work around ARM 541 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 542 to a coherent interconnect. 543 544 If a Cortex-A53 processor is executing a store or prefetch for 545 write instruction at the same time as a processor in another 546 cluster is executing a cache maintenance operation to the same 547 address, then this erratum might cause a clean cache line to be 548 incorrectly marked as dirty. 549 550 The workaround promotes data cache clean instructions to 551 data cache clean-and-invalidate. 552 Please note that this option does not necessarily enable the 553 workaround, as it depends on the alternative framework, which will 554 only patch the kernel if an affected CPU is detected. 555 556 If unsure, say Y. 557 558config ARM64_ERRATUM_819472 559 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 560 default y 561 select ARM64_WORKAROUND_CLEAN_CACHE 562 help 563 This option adds an alternative code sequence to work around ARM 564 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 565 present when it is connected to a coherent interconnect. 566 567 If the processor is executing a load and store exclusive sequence at 568 the same time as a processor in another cluster is executing a cache 569 maintenance operation to the same address, then this erratum might 570 cause data corruption. 571 572 The workaround promotes data cache clean instructions to 573 data cache clean-and-invalidate. 574 Please note that this does not necessarily enable the workaround, 575 as it depends on the alternative framework, which will only patch 576 the kernel if an affected CPU is detected. 577 578 If unsure, say Y. 579 580config ARM64_ERRATUM_832075 581 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 582 default y 583 help 584 This option adds an alternative code sequence to work around ARM 585 erratum 832075 on Cortex-A57 parts up to r1p2. 586 587 Affected Cortex-A57 parts might deadlock when exclusive load/store 588 instructions to Write-Back memory are mixed with Device loads. 589 590 The workaround is to promote device loads to use Load-Acquire 591 semantics. 592 Please note that this does not necessarily enable the workaround, 593 as it depends on the alternative framework, which will only patch 594 the kernel if an affected CPU is detected. 595 596 If unsure, say Y. 597 598config ARM64_ERRATUM_834220 599 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 600 depends on KVM 601 help 602 This option adds an alternative code sequence to work around ARM 603 erratum 834220 on Cortex-A57 parts up to r1p2. 604 605 Affected Cortex-A57 parts might report a Stage 2 translation 606 fault as the result of a Stage 1 fault for load crossing a 607 page boundary when there is a permission or device memory 608 alignment fault at Stage 1 and a translation fault at Stage 2. 609 610 The workaround is to verify that the Stage 1 translation 611 doesn't generate a fault before handling the Stage 2 fault. 612 Please note that this does not necessarily enable the workaround, 613 as it depends on the alternative framework, which will only patch 614 the kernel if an affected CPU is detected. 615 616 If unsure, say N. 617 618config ARM64_ERRATUM_1742098 619 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 620 depends on COMPAT 621 default y 622 help 623 This option removes the AES hwcap for aarch32 user-space to 624 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 625 626 Affected parts may corrupt the AES state if an interrupt is 627 taken between a pair of AES instructions. These instructions 628 are only present if the cryptography extensions are present. 629 All software should have a fallback implementation for CPUs 630 that don't implement the cryptography extensions. 631 632 If unsure, say Y. 633 634config ARM64_ERRATUM_845719 635 bool "Cortex-A53: 845719: a load might read incorrect data" 636 depends on COMPAT 637 default y 638 help 639 This option adds an alternative code sequence to work around ARM 640 erratum 845719 on Cortex-A53 parts up to r0p4. 641 642 When running a compat (AArch32) userspace on an affected Cortex-A53 643 part, a load at EL0 from a virtual address that matches the bottom 32 644 bits of the virtual address used by a recent load at (AArch64) EL1 645 might return incorrect data. 646 647 The workaround is to write the contextidr_el1 register on exception 648 return to a 32-bit task. 649 Please note that this does not necessarily enable the workaround, 650 as it depends on the alternative framework, which will only patch 651 the kernel if an affected CPU is detected. 652 653 If unsure, say Y. 654 655config ARM64_ERRATUM_843419 656 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 657 default y 658 help 659 This option links the kernel with '--fix-cortex-a53-843419' and 660 enables PLT support to replace certain ADRP instructions, which can 661 cause subsequent memory accesses to use an incorrect address on 662 Cortex-A53 parts up to r0p4. 663 664 If unsure, say Y. 665 666config ARM64_ERRATUM_1024718 667 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 668 default y 669 help 670 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 671 672 Affected Cortex-A55 cores (all revisions) could cause incorrect 673 update of the hardware dirty bit when the DBM/AP bits are updated 674 without a break-before-make. The workaround is to disable the usage 675 of hardware DBM locally on the affected cores. CPUs not affected by 676 this erratum will continue to use the feature. 677 678 If unsure, say Y. 679 680config ARM64_ERRATUM_1418040 681 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 682 default y 683 depends on COMPAT 684 help 685 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 686 errata 1188873 and 1418040. 687 688 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 689 cause register corruption when accessing the timer registers 690 from AArch32 userspace. 691 692 If unsure, say Y. 693 694config ARM64_WORKAROUND_SPECULATIVE_AT 695 bool 696 697config ARM64_ERRATUM_1165522 698 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 699 default y 700 select ARM64_WORKAROUND_SPECULATIVE_AT 701 help 702 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 703 704 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 705 corrupted TLBs by speculating an AT instruction during a guest 706 context switch. 707 708 If unsure, say Y. 709 710config ARM64_ERRATUM_1319367 711 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 712 default y 713 select ARM64_WORKAROUND_SPECULATIVE_AT 714 help 715 This option adds work arounds for ARM Cortex-A57 erratum 1319537 716 and A72 erratum 1319367 717 718 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 719 speculating an AT instruction during a guest context switch. 720 721 If unsure, say Y. 722 723config ARM64_ERRATUM_1530923 724 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 725 default y 726 select ARM64_WORKAROUND_SPECULATIVE_AT 727 help 728 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 729 730 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 731 corrupted TLBs by speculating an AT instruction during a guest 732 context switch. 733 734 If unsure, say Y. 735 736config ARM64_WORKAROUND_REPEAT_TLBI 737 bool 738 739config ARM64_ERRATUM_2441007 740 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 741 select ARM64_WORKAROUND_REPEAT_TLBI 742 help 743 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 744 745 Under very rare circumstances, affected Cortex-A55 CPUs 746 may not handle a race between a break-before-make sequence on one 747 CPU, and another CPU accessing the same page. This could allow a 748 store to a page that has been unmapped. 749 750 Work around this by adding the affected CPUs to the list that needs 751 TLB sequences to be done twice. 752 753 If unsure, say N. 754 755config ARM64_ERRATUM_1286807 756 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 757 select ARM64_WORKAROUND_REPEAT_TLBI 758 help 759 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 760 761 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 762 address for a cacheable mapping of a location is being 763 accessed by a core while another core is remapping the virtual 764 address to a new physical page using the recommended 765 break-before-make sequence, then under very rare circumstances 766 TLBI+DSB completes before a read using the translation being 767 invalidated has been observed by other observers. The 768 workaround repeats the TLBI+DSB operation. 769 770 If unsure, say N. 771 772config ARM64_ERRATUM_1463225 773 bool "Cortex-A76: Software Step might prevent interrupt recognition" 774 default y 775 help 776 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 777 778 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 779 of a system call instruction (SVC) can prevent recognition of 780 subsequent interrupts when software stepping is disabled in the 781 exception handler of the system call and either kernel debugging 782 is enabled or VHE is in use. 783 784 Work around the erratum by triggering a dummy step exception 785 when handling a system call from a task that is being stepped 786 in a VHE configuration of the kernel. 787 788 If unsure, say Y. 789 790config ARM64_ERRATUM_1542419 791 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 792 help 793 This option adds a workaround for ARM Neoverse-N1 erratum 794 1542419. 795 796 Affected Neoverse-N1 cores could execute a stale instruction when 797 modified by another CPU. The workaround depends on a firmware 798 counterpart. 799 800 Workaround the issue by hiding the DIC feature from EL0. This 801 forces user-space to perform cache maintenance. 802 803 If unsure, say N. 804 805config ARM64_ERRATUM_1508412 806 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 807 default y 808 help 809 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 810 811 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 812 of a store-exclusive or read of PAR_EL1 and a load with device or 813 non-cacheable memory attributes. The workaround depends on a firmware 814 counterpart. 815 816 KVM guests must also have the workaround implemented or they can 817 deadlock the system. 818 819 Work around the issue by inserting DMB SY barriers around PAR_EL1 820 register reads and warning KVM users. The DMB barrier is sufficient 821 to prevent a speculative PAR_EL1 read. 822 823 If unsure, say Y. 824 825config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 826 bool 827 828config ARM64_ERRATUM_2051678 829 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 830 default y 831 help 832 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 833 Affected Cortex-A510 might not respect the ordering rules for 834 hardware update of the page table's dirty bit. The workaround 835 is to not enable the feature on affected CPUs. 836 837 If unsure, say Y. 838 839config ARM64_ERRATUM_2077057 840 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 841 default y 842 help 843 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 844 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 845 expected, but a Pointer Authentication trap is taken instead. The 846 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 847 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 848 849 This can only happen when EL2 is stepping EL1. 850 851 When these conditions occur, the SPSR_EL2 value is unchanged from the 852 previous guest entry, and can be restored from the in-memory copy. 853 854 If unsure, say Y. 855 856config ARM64_ERRATUM_2658417 857 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 858 default y 859 help 860 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 861 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 862 BFMMLA or VMMLA instructions in rare circumstances when a pair of 863 A510 CPUs are using shared neon hardware. As the sharing is not 864 discoverable by the kernel, hide the BF16 HWCAP to indicate that 865 user-space should not be using these instructions. 866 867 If unsure, say Y. 868 869config ARM64_ERRATUM_2119858 870 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 871 default y 872 depends on CORESIGHT_TRBE 873 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 874 help 875 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 876 877 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 878 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 879 the event of a WRAP event. 880 881 Work around the issue by always making sure we move the TRBPTR_EL1 by 882 256 bytes before enabling the buffer and filling the first 256 bytes of 883 the buffer with ETM ignore packets upon disabling. 884 885 If unsure, say Y. 886 887config ARM64_ERRATUM_2139208 888 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 889 default y 890 depends on CORESIGHT_TRBE 891 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 892 help 893 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 894 895 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 896 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 897 the event of a WRAP event. 898 899 Work around the issue by always making sure we move the TRBPTR_EL1 by 900 256 bytes before enabling the buffer and filling the first 256 bytes of 901 the buffer with ETM ignore packets upon disabling. 902 903 If unsure, say Y. 904 905config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 906 bool 907 908config ARM64_ERRATUM_2054223 909 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 910 default y 911 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 912 help 913 Enable workaround for ARM Cortex-A710 erratum 2054223 914 915 Affected cores may fail to flush the trace data on a TSB instruction, when 916 the PE is in trace prohibited state. This will cause losing a few bytes 917 of the trace cached. 918 919 Workaround is to issue two TSB consecutively on affected cores. 920 921 If unsure, say Y. 922 923config ARM64_ERRATUM_2067961 924 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 925 default y 926 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 927 help 928 Enable workaround for ARM Neoverse-N2 erratum 2067961 929 930 Affected cores may fail to flush the trace data on a TSB instruction, when 931 the PE is in trace prohibited state. This will cause losing a few bytes 932 of the trace cached. 933 934 Workaround is to issue two TSB consecutively on affected cores. 935 936 If unsure, say Y. 937 938config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 939 bool 940 941config ARM64_ERRATUM_2253138 942 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 943 depends on CORESIGHT_TRBE 944 default y 945 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 946 help 947 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 948 949 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 950 for TRBE. Under some conditions, the TRBE might generate a write to the next 951 virtually addressed page following the last page of the TRBE address space 952 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 953 954 Work around this in the driver by always making sure that there is a 955 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 956 957 If unsure, say Y. 958 959config ARM64_ERRATUM_2224489 960 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 961 depends on CORESIGHT_TRBE 962 default y 963 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 964 help 965 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 966 967 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 968 for TRBE. Under some conditions, the TRBE might generate a write to the next 969 virtually addressed page following the last page of the TRBE address space 970 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 971 972 Work around this in the driver by always making sure that there is a 973 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 974 975 If unsure, say Y. 976 977config ARM64_ERRATUM_2441009 978 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 979 select ARM64_WORKAROUND_REPEAT_TLBI 980 help 981 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 982 983 Under very rare circumstances, affected Cortex-A510 CPUs 984 may not handle a race between a break-before-make sequence on one 985 CPU, and another CPU accessing the same page. This could allow a 986 store to a page that has been unmapped. 987 988 Work around this by adding the affected CPUs to the list that needs 989 TLB sequences to be done twice. 990 991 If unsure, say N. 992 993config ARM64_ERRATUM_2064142 994 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 995 depends on CORESIGHT_TRBE 996 default y 997 help 998 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 999 1000 Affected Cortex-A510 core might fail to write into system registers after the 1001 TRBE has been disabled. Under some conditions after the TRBE has been disabled 1002 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 1003 and TRBTRG_EL1 will be ignored and will not be effected. 1004 1005 Work around this in the driver by executing TSB CSYNC and DSB after collection 1006 is stopped and before performing a system register write to one of the affected 1007 registers. 1008 1009 If unsure, say Y. 1010 1011config ARM64_ERRATUM_2038923 1012 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 1013 depends on CORESIGHT_TRBE 1014 default y 1015 help 1016 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 1017 1018 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 1019 prohibited within the CPU. As a result, the trace buffer or trace buffer state 1020 might be corrupted. This happens after TRBE buffer has been enabled by setting 1021 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 1022 execution changes from a context, in which trace is prohibited to one where it 1023 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1024 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1025 the trace buffer state might be corrupted. 1026 1027 Work around this in the driver by preventing an inconsistent view of whether the 1028 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1029 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1030 two ISB instructions if no ERET is to take place. 1031 1032 If unsure, say Y. 1033 1034config ARM64_ERRATUM_1902691 1035 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1036 depends on CORESIGHT_TRBE 1037 default y 1038 help 1039 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1040 1041 Affected Cortex-A510 core might cause trace data corruption, when being written 1042 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1043 trace data. 1044 1045 Work around this problem in the driver by just preventing TRBE initialization on 1046 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1047 on such implementations. This will cover the kernel for any firmware that doesn't 1048 do this already. 1049 1050 If unsure, say Y. 1051 1052config ARM64_ERRATUM_2457168 1053 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1054 depends on ARM64_AMU_EXTN 1055 default y 1056 help 1057 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1058 1059 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1060 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1061 incorrectly giving a significantly higher output value. 1062 1063 Work around this problem by returning 0 when reading the affected counter in 1064 key locations that results in disabling all users of this counter. This effect 1065 is the same to firmware disabling affected counters. 1066 1067 If unsure, say Y. 1068 1069config ARM64_ERRATUM_2645198 1070 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1071 default y 1072 help 1073 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1074 1075 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1076 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1077 next instruction abort caused by permission fault. 1078 1079 Only user-space does executable to non-executable permission transition via 1080 mprotect() system call. Workaround the problem by doing a break-before-make 1081 TLB invalidation, for all changes to executable user space mappings. 1082 1083 If unsure, say Y. 1084 1085config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1086 bool 1087 1088config ARM64_ERRATUM_2966298 1089 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1090 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1091 default y 1092 help 1093 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1094 1095 On an affected Cortex-A520 core, a speculatively executed unprivileged 1096 load might leak data from a privileged level via a cache side channel. 1097 1098 Work around this problem by executing a TLBI before returning to EL0. 1099 1100 If unsure, say Y. 1101 1102config ARM64_ERRATUM_3117295 1103 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1104 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1105 default y 1106 help 1107 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1108 1109 On an affected Cortex-A510 core, a speculatively executed unprivileged 1110 load might leak data from a privileged level via a cache side channel. 1111 1112 Work around this problem by executing a TLBI before returning to EL0. 1113 1114 If unsure, say Y. 1115 1116config ARM64_ERRATUM_3194386 1117 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1118 default y 1119 help 1120 This option adds the workaround for the following errata: 1121 1122 * ARM Cortex-A76 erratum 3324349 1123 * ARM Cortex-A77 erratum 3324348 1124 * ARM Cortex-A78 erratum 3324344 1125 * ARM Cortex-A78C erratum 3324346 1126 * ARM Cortex-A78C erratum 3324347 1127 * ARM Cortex-A710 erratam 3324338 1128 * ARM Cortex-A715 errartum 3456084 1129 * ARM Cortex-A720 erratum 3456091 1130 * ARM Cortex-A725 erratum 3456106 1131 * ARM Cortex-X1 erratum 3324344 1132 * ARM Cortex-X1C erratum 3324346 1133 * ARM Cortex-X2 erratum 3324338 1134 * ARM Cortex-X3 erratum 3324335 1135 * ARM Cortex-X4 erratum 3194386 1136 * ARM Cortex-X925 erratum 3324334 1137 * ARM Neoverse-N1 erratum 3324349 1138 * ARM Neoverse N2 erratum 3324339 1139 * ARM Neoverse-N3 erratum 3456111 1140 * ARM Neoverse-V1 erratum 3324341 1141 * ARM Neoverse V2 erratum 3324336 1142 * ARM Neoverse-V3 erratum 3312417 1143 * ARM Neoverse-V3AE erratum 3312417 1144 1145 On affected cores "MSR SSBS, #0" instructions may not affect 1146 subsequent speculative instructions, which may permit unexepected 1147 speculative store bypassing. 1148 1149 Work around this problem by placing a Speculation Barrier (SB) or 1150 Instruction Synchronization Barrier (ISB) after kernel changes to 1151 SSBS. The presence of the SSBS special-purpose register is hidden 1152 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1153 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1154 1155 If unsure, say Y. 1156 1157config CAVIUM_ERRATUM_22375 1158 bool "Cavium erratum 22375, 24313" 1159 default y 1160 help 1161 Enable workaround for errata 22375 and 24313. 1162 1163 This implements two gicv3-its errata workarounds for ThunderX. Both 1164 with a small impact affecting only ITS table allocation. 1165 1166 erratum 22375: only alloc 8MB table size 1167 erratum 24313: ignore memory access type 1168 1169 The fixes are in ITS initialization and basically ignore memory access 1170 type and table size provided by the TYPER and BASER registers. 1171 1172 If unsure, say Y. 1173 1174config CAVIUM_ERRATUM_23144 1175 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1176 depends on NUMA 1177 default y 1178 help 1179 ITS SYNC command hang for cross node io and collections/cpu mapping. 1180 1181 If unsure, say Y. 1182 1183config CAVIUM_ERRATUM_23154 1184 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1185 default y 1186 help 1187 The ThunderX GICv3 implementation requires a modified version for 1188 reading the IAR status to ensure data synchronization 1189 (access to icc_iar1_el1 is not sync'ed before and after). 1190 1191 It also suffers from erratum 38545 (also present on Marvell's 1192 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1193 spuriously presented to the CPU interface. 1194 1195 If unsure, say Y. 1196 1197config CAVIUM_ERRATUM_27456 1198 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1199 default y 1200 help 1201 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1202 instructions may cause the icache to become corrupted if it 1203 contains data for a non-current ASID. The fix is to 1204 invalidate the icache when changing the mm context. 1205 1206 If unsure, say Y. 1207 1208config CAVIUM_ERRATUM_30115 1209 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1210 default y 1211 help 1212 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1213 1.2, and T83 Pass 1.0, KVM guest execution may disable 1214 interrupts in host. Trapping both GICv3 group-0 and group-1 1215 accesses sidesteps the issue. 1216 1217 If unsure, say Y. 1218 1219config CAVIUM_TX2_ERRATUM_219 1220 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1221 default y 1222 help 1223 On Cavium ThunderX2, a load, store or prefetch instruction between a 1224 TTBR update and the corresponding context synchronizing operation can 1225 cause a spurious Data Abort to be delivered to any hardware thread in 1226 the CPU core. 1227 1228 Work around the issue by avoiding the problematic code sequence and 1229 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1230 trap handler performs the corresponding register access, skips the 1231 instruction and ensures context synchronization by virtue of the 1232 exception return. 1233 1234 If unsure, say Y. 1235 1236config FUJITSU_ERRATUM_010001 1237 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1238 default y 1239 help 1240 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1241 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1242 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1243 This fault occurs under a specific hardware condition when a 1244 load/store instruction performs an address translation using: 1245 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1246 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1247 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1248 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1249 1250 The workaround is to ensure these bits are clear in TCR_ELx. 1251 The workaround only affects the Fujitsu-A64FX. 1252 1253 If unsure, say Y. 1254 1255config HISILICON_ERRATUM_161600802 1256 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1257 default y 1258 help 1259 The HiSilicon Hip07 SoC uses the wrong redistributor base 1260 when issued ITS commands such as VMOVP and VMAPP, and requires 1261 a 128kB offset to be applied to the target address in this commands. 1262 1263 If unsure, say Y. 1264 1265config HISILICON_ERRATUM_162100801 1266 bool "Hip09 162100801 erratum support" 1267 default y 1268 help 1269 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1270 during unmapping operation, which will cause some vSGIs lost. 1271 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1272 after VMOVP. 1273 1274 If unsure, say Y. 1275 1276config QCOM_FALKOR_ERRATUM_1003 1277 bool "Falkor E1003: Incorrect translation due to ASID change" 1278 default y 1279 help 1280 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1281 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1282 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1283 then only for entries in the walk cache, since the leaf translation 1284 is unchanged. Work around the erratum by invalidating the walk cache 1285 entries for the trampoline before entering the kernel proper. 1286 1287config QCOM_FALKOR_ERRATUM_1009 1288 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1289 default y 1290 select ARM64_WORKAROUND_REPEAT_TLBI 1291 help 1292 On Falkor v1, the CPU may prematurely complete a DSB following a 1293 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1294 one more time to fix the issue. 1295 1296 If unsure, say Y. 1297 1298config QCOM_QDF2400_ERRATUM_0065 1299 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1300 default y 1301 help 1302 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1303 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1304 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1305 1306 If unsure, say Y. 1307 1308config QCOM_FALKOR_ERRATUM_E1041 1309 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1310 default y 1311 help 1312 Falkor CPU may speculatively fetch instructions from an improper 1313 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1314 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1315 1316 If unsure, say Y. 1317 1318config NVIDIA_CARMEL_CNP_ERRATUM 1319 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1320 default y 1321 help 1322 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1323 invalidate shared TLB entries installed by a different core, as it would 1324 on standard ARM cores. 1325 1326 If unsure, say Y. 1327 1328config ROCKCHIP_ERRATUM_3568002 1329 bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" 1330 default y 1331 help 1332 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI 1333 addressing limited to the first 32bit of physical address space. 1334 1335 If unsure, say Y. 1336 1337config ROCKCHIP_ERRATUM_3588001 1338 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1339 default y 1340 help 1341 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1342 This means, that its sharability feature may not be used, even though it 1343 is supported by the IP itself. 1344 1345 If unsure, say Y. 1346 1347config SOCIONEXT_SYNQUACER_PREITS 1348 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1349 default y 1350 help 1351 Socionext Synquacer SoCs implement a separate h/w block to generate 1352 MSI doorbell writes with non-zero values for the device ID. 1353 1354 If unsure, say Y. 1355 1356endmenu # "ARM errata workarounds via the alternatives framework" 1357 1358choice 1359 prompt "Page size" 1360 default ARM64_4K_PAGES 1361 help 1362 Page size (translation granule) configuration. 1363 1364config ARM64_4K_PAGES 1365 bool "4KB" 1366 select HAVE_PAGE_SIZE_4KB 1367 help 1368 This feature enables 4KB pages support. 1369 1370config ARM64_16K_PAGES 1371 bool "16KB" 1372 select HAVE_PAGE_SIZE_16KB 1373 help 1374 The system will use 16KB pages support. AArch32 emulation 1375 requires applications compiled with 16K (or a multiple of 16K) 1376 aligned segments. 1377 1378config ARM64_64K_PAGES 1379 bool "64KB" 1380 select HAVE_PAGE_SIZE_64KB 1381 help 1382 This feature enables 64KB pages support (4KB by default) 1383 allowing only two levels of page tables and faster TLB 1384 look-up. AArch32 emulation requires applications compiled 1385 with 64K aligned segments. 1386 1387endchoice 1388 1389choice 1390 prompt "Virtual address space size" 1391 default ARM64_VA_BITS_52 1392 help 1393 Allows choosing one of multiple possible virtual address 1394 space sizes. The level of translation table is determined by 1395 a combination of page size and virtual address space size. 1396 1397config ARM64_VA_BITS_36 1398 bool "36-bit" if EXPERT 1399 depends on PAGE_SIZE_16KB 1400 1401config ARM64_VA_BITS_39 1402 bool "39-bit" 1403 depends on PAGE_SIZE_4KB 1404 1405config ARM64_VA_BITS_42 1406 bool "42-bit" 1407 depends on PAGE_SIZE_64KB 1408 1409config ARM64_VA_BITS_47 1410 bool "47-bit" 1411 depends on PAGE_SIZE_16KB 1412 1413config ARM64_VA_BITS_48 1414 bool "48-bit" 1415 1416config ARM64_VA_BITS_52 1417 bool "52-bit" 1418 help 1419 Enable 52-bit virtual addressing for userspace when explicitly 1420 requested via a hint to mmap(). The kernel will also use 52-bit 1421 virtual addresses for its own mappings (provided HW support for 1422 this feature is available, otherwise it reverts to 48-bit). 1423 1424 NOTE: Enabling 52-bit virtual addressing in conjunction with 1425 ARMv8.3 Pointer Authentication will result in the PAC being 1426 reduced from 7 bits to 3 bits, which may have a significant 1427 impact on its susceptibility to brute-force attacks. 1428 1429 If unsure, select 48-bit virtual addressing instead. 1430 1431endchoice 1432 1433config ARM64_FORCE_52BIT 1434 bool "Force 52-bit virtual addresses for userspace" 1435 depends on ARM64_VA_BITS_52 && EXPERT 1436 help 1437 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1438 to maintain compatibility with older software by providing 48-bit VAs 1439 unless a hint is supplied to mmap. 1440 1441 This configuration option disables the 48-bit compatibility logic, and 1442 forces all userspace addresses to be 52-bit on HW that supports it. One 1443 should only enable this configuration option for stress testing userspace 1444 memory management code. If unsure say N here. 1445 1446config ARM64_VA_BITS 1447 int 1448 default 36 if ARM64_VA_BITS_36 1449 default 39 if ARM64_VA_BITS_39 1450 default 42 if ARM64_VA_BITS_42 1451 default 47 if ARM64_VA_BITS_47 1452 default 48 if ARM64_VA_BITS_48 1453 default 52 if ARM64_VA_BITS_52 1454 1455choice 1456 prompt "Physical address space size" 1457 default ARM64_PA_BITS_48 1458 help 1459 Choose the maximum physical address range that the kernel will 1460 support. 1461 1462config ARM64_PA_BITS_48 1463 bool "48-bit" 1464 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1465 1466config ARM64_PA_BITS_52 1467 bool "52-bit" 1468 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1469 help 1470 Enable support for a 52-bit physical address space, introduced as 1471 part of the ARMv8.2-LPA extension. 1472 1473 With this enabled, the kernel will also continue to work on CPUs that 1474 do not support ARMv8.2-LPA, but with some added memory overhead (and 1475 minor performance overhead). 1476 1477endchoice 1478 1479config ARM64_PA_BITS 1480 int 1481 default 48 if ARM64_PA_BITS_48 1482 default 52 if ARM64_PA_BITS_52 1483 1484config ARM64_LPA2 1485 def_bool y 1486 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1487 1488choice 1489 prompt "Endianness" 1490 default CPU_LITTLE_ENDIAN 1491 help 1492 Select the endianness of data accesses performed by the CPU. Userspace 1493 applications will need to be compiled and linked for the endianness 1494 that is selected here. 1495 1496config CPU_BIG_ENDIAN 1497 bool "Build big-endian kernel" 1498 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1499 depends on (AS_IS_GNU || AS_VERSION >= 150000) && BROKEN 1500 help 1501 Say Y if you plan on running a kernel with a big-endian userspace. 1502 1503config CPU_LITTLE_ENDIAN 1504 bool "Build little-endian kernel" 1505 help 1506 Say Y if you plan on running a kernel with a little-endian userspace. 1507 This is usually the case for distributions targeting arm64. 1508 1509endchoice 1510 1511config NR_CPUS 1512 int "Maximum number of CPUs (2-4096)" 1513 range 2 4096 1514 default "512" 1515 1516config HOTPLUG_CPU 1517 bool "Support for hot-pluggable CPUs" 1518 select GENERIC_IRQ_MIGRATION 1519 help 1520 Say Y here to experiment with turning CPUs off and on. CPUs 1521 can be controlled through /sys/devices/system/cpu. 1522 1523# Common NUMA Features 1524config NUMA 1525 bool "NUMA Memory Allocation and Scheduler Support" 1526 select GENERIC_ARCH_NUMA 1527 select OF_NUMA 1528 select HAVE_SETUP_PER_CPU_AREA 1529 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1530 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1531 select USE_PERCPU_NUMA_NODE_ID 1532 help 1533 Enable NUMA (Non-Uniform Memory Access) support. 1534 1535 The kernel will try to allocate memory used by a CPU on the 1536 local memory of the CPU and add some more 1537 NUMA awareness to the kernel. 1538 1539config NODES_SHIFT 1540 int "Maximum NUMA Nodes (as a power of 2)" 1541 range 1 10 1542 default "4" 1543 depends on NUMA 1544 help 1545 Specify the maximum number of NUMA Nodes available on the target 1546 system. Increases memory reserved to accommodate various tables. 1547 1548source "kernel/Kconfig.hz" 1549 1550config ARCH_SPARSEMEM_ENABLE 1551 def_bool y 1552 select SPARSEMEM_VMEMMAP_ENABLE 1553 select SPARSEMEM_VMEMMAP 1554 1555config HW_PERF_EVENTS 1556 def_bool y 1557 depends on ARM_PMU 1558 1559# Supported by clang >= 7.0 or GCC >= 12.0.0 1560config CC_HAVE_SHADOW_CALL_STACK 1561 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1562 1563config PARAVIRT 1564 bool "Enable paravirtualization code" 1565 help 1566 This changes the kernel so it can modify itself when it is run 1567 under a hypervisor, potentially improving performance significantly 1568 over full virtualization. 1569 1570config PARAVIRT_TIME_ACCOUNTING 1571 bool "Paravirtual steal time accounting" 1572 select PARAVIRT 1573 help 1574 Select this option to enable fine granularity task steal time 1575 accounting. Time spent executing other tasks in parallel with 1576 the current vCPU is discounted from the vCPU power. To account for 1577 that, there can be a small performance impact. 1578 1579 If in doubt, say N here. 1580 1581config ARCH_SUPPORTS_KEXEC 1582 def_bool PM_SLEEP_SMP 1583 1584config ARCH_SUPPORTS_KEXEC_FILE 1585 def_bool y 1586 1587config ARCH_SELECTS_KEXEC_FILE 1588 def_bool y 1589 depends on KEXEC_FILE 1590 select HAVE_IMA_KEXEC if IMA 1591 1592config ARCH_SUPPORTS_KEXEC_SIG 1593 def_bool y 1594 1595config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1596 def_bool y 1597 1598config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1599 def_bool y 1600 1601config ARCH_SUPPORTS_KEXEC_HANDOVER 1602 def_bool y 1603 1604config ARCH_SUPPORTS_CRASH_DUMP 1605 def_bool y 1606 1607config ARCH_DEFAULT_CRASH_DUMP 1608 def_bool y 1609 1610config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1611 def_bool CRASH_RESERVE 1612 1613config TRANS_TABLE 1614 def_bool y 1615 depends on HIBERNATION || KEXEC_CORE 1616 1617config XEN_DOM0 1618 def_bool y 1619 depends on XEN 1620 1621config XEN 1622 bool "Xen guest support on ARM64" 1623 depends on ARM64 && OF 1624 select SWIOTLB_XEN 1625 select PARAVIRT 1626 help 1627 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1628 1629# include/linux/mmzone.h requires the following to be true: 1630# 1631# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1632# 1633# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1634# 1635# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1636# ----+-------------------+--------------+----------------------+-------------------------+ 1637# 4K | 27 | 12 | 15 | 10 | 1638# 16K | 27 | 14 | 13 | 11 | 1639# 64K | 29 | 16 | 13 | 13 | 1640config ARCH_FORCE_MAX_ORDER 1641 int 1642 default "13" if ARM64_64K_PAGES 1643 default "11" if ARM64_16K_PAGES 1644 default "10" 1645 help 1646 The kernel page allocator limits the size of maximal physically 1647 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1648 defines the maximal power of two of number of pages that can be 1649 allocated as a single contiguous block. This option allows 1650 overriding the default setting when ability to allocate very 1651 large blocks of physically contiguous memory is required. 1652 1653 The maximal size of allocation cannot exceed the size of the 1654 section, so the value of MAX_PAGE_ORDER should satisfy 1655 1656 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1657 1658 Don't change if unsure. 1659 1660config UNMAP_KERNEL_AT_EL0 1661 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1662 default y 1663 help 1664 Speculation attacks against some high-performance processors can 1665 be used to bypass MMU permission checks and leak kernel data to 1666 userspace. This can be defended against by unmapping the kernel 1667 when running in userspace, mapping it back in on exception entry 1668 via a trampoline page in the vector table. 1669 1670 If unsure, say Y. 1671 1672config MITIGATE_SPECTRE_BRANCH_HISTORY 1673 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1674 default y 1675 help 1676 Speculation attacks against some high-performance processors can 1677 make use of branch history to influence future speculation. 1678 When taking an exception from user-space, a sequence of branches 1679 or a firmware call overwrites the branch history. 1680 1681config ARM64_SW_TTBR0_PAN 1682 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1683 depends on !KCSAN 1684 select ARM64_PAN 1685 help 1686 Enabling this option prevents the kernel from accessing 1687 user-space memory directly by pointing TTBR0_EL1 to a reserved 1688 zeroed area and reserved ASID. The user access routines 1689 restore the valid TTBR0_EL1 temporarily. 1690 1691config ARM64_TAGGED_ADDR_ABI 1692 bool "Enable the tagged user addresses syscall ABI" 1693 default y 1694 help 1695 When this option is enabled, user applications can opt in to a 1696 relaxed ABI via prctl() allowing tagged addresses to be passed 1697 to system calls as pointer arguments. For details, see 1698 Documentation/arch/arm64/tagged-address-abi.rst. 1699 1700menuconfig COMPAT 1701 bool "Kernel support for 32-bit EL0" 1702 depends on ARM64_4K_PAGES || EXPERT 1703 select HAVE_UID16 1704 select OLD_SIGSUSPEND3 1705 select COMPAT_OLD_SIGACTION 1706 help 1707 This option enables support for a 32-bit EL0 running under a 64-bit 1708 kernel at EL1. AArch32-specific components such as system calls, 1709 the user helper functions, VFP support and the ptrace interface are 1710 handled appropriately by the kernel. 1711 1712 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1713 that you will only be able to execute AArch32 binaries that were compiled 1714 with page size aligned segments. 1715 1716 If you want to execute 32-bit userspace applications, say Y. 1717 1718if COMPAT 1719 1720config KUSER_HELPERS 1721 bool "Enable kuser helpers page for 32-bit applications" 1722 default y 1723 help 1724 Warning: disabling this option may break 32-bit user programs. 1725 1726 Provide kuser helpers to compat tasks. The kernel provides 1727 helper code to userspace in read only form at a fixed location 1728 to allow userspace to be independent of the CPU type fitted to 1729 the system. This permits binaries to be run on ARMv4 through 1730 to ARMv8 without modification. 1731 1732 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1733 1734 However, the fixed address nature of these helpers can be used 1735 by ROP (return orientated programming) authors when creating 1736 exploits. 1737 1738 If all of the binaries and libraries which run on your platform 1739 are built specifically for your platform, and make no use of 1740 these helpers, then you can turn this option off to hinder 1741 such exploits. However, in that case, if a binary or library 1742 relying on those helpers is run, it will not function correctly. 1743 1744 Say N here only if you are absolutely certain that you do not 1745 need these helpers; otherwise, the safe option is to say Y. 1746 1747config COMPAT_VDSO 1748 bool "Enable vDSO for 32-bit applications" 1749 depends on !CPU_BIG_ENDIAN 1750 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1751 default y 1752 help 1753 Place in the process address space of 32-bit applications an 1754 ELF shared object providing fast implementations of gettimeofday 1755 and clock_gettime. 1756 1757 You must have a 32-bit build of glibc 2.22 or later for programs 1758 to seamlessly take advantage of this. 1759 1760config THUMB2_COMPAT_VDSO 1761 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1762 depends on COMPAT_VDSO 1763 default y 1764 help 1765 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1766 otherwise with '-marm'. 1767 1768config COMPAT_ALIGNMENT_FIXUPS 1769 bool "Fix up misaligned multi-word loads and stores in user space" 1770 1771menuconfig ARMV8_DEPRECATED 1772 bool "Emulate deprecated/obsolete ARMv8 instructions" 1773 depends on SYSCTL 1774 help 1775 Legacy software support may require certain instructions 1776 that have been deprecated or obsoleted in the architecture. 1777 1778 Enable this config to enable selective emulation of these 1779 features. 1780 1781 If unsure, say Y 1782 1783if ARMV8_DEPRECATED 1784 1785config SWP_EMULATION 1786 bool "Emulate SWP/SWPB instructions" 1787 help 1788 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1789 they are always undefined. Say Y here to enable software 1790 emulation of these instructions for userspace using LDXR/STXR. 1791 This feature can be controlled at runtime with the abi.swp 1792 sysctl which is disabled by default. 1793 1794 In some older versions of glibc [<=2.8] SWP is used during futex 1795 trylock() operations with the assumption that the code will not 1796 be preempted. This invalid assumption may be more likely to fail 1797 with SWP emulation enabled, leading to deadlock of the user 1798 application. 1799 1800 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1801 on an external transaction monitoring block called a global 1802 monitor to maintain update atomicity. If your system does not 1803 implement a global monitor, this option can cause programs that 1804 perform SWP operations to uncached memory to deadlock. 1805 1806 If unsure, say Y 1807 1808config CP15_BARRIER_EMULATION 1809 bool "Emulate CP15 Barrier instructions" 1810 help 1811 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1812 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1813 strongly recommended to use the ISB, DSB, and DMB 1814 instructions instead. 1815 1816 Say Y here to enable software emulation of these 1817 instructions for AArch32 userspace code. When this option is 1818 enabled, CP15 barrier usage is traced which can help 1819 identify software that needs updating. This feature can be 1820 controlled at runtime with the abi.cp15_barrier sysctl. 1821 1822 If unsure, say Y 1823 1824config SETEND_EMULATION 1825 bool "Emulate SETEND instruction" 1826 help 1827 The SETEND instruction alters the data-endianness of the 1828 AArch32 EL0, and is deprecated in ARMv8. 1829 1830 Say Y here to enable software emulation of the instruction 1831 for AArch32 userspace code. This feature can be controlled 1832 at runtime with the abi.setend sysctl. 1833 1834 Note: All the cpus on the system must have mixed endian support at EL0 1835 for this feature to be enabled. If a new CPU - which doesn't support mixed 1836 endian - is hotplugged in after this feature has been enabled, there could 1837 be unexpected results in the applications. 1838 1839 If unsure, say Y 1840endif # ARMV8_DEPRECATED 1841 1842endif # COMPAT 1843 1844menu "ARMv8.1 architectural features" 1845 1846config ARM64_HW_AFDBM 1847 bool "Support for hardware updates of the Access and Dirty page flags" 1848 default y 1849 help 1850 The ARMv8.1 architecture extensions introduce support for 1851 hardware updates of the access and dirty information in page 1852 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1853 capable processors, accesses to pages with PTE_AF cleared will 1854 set this bit instead of raising an access flag fault. 1855 Similarly, writes to read-only pages with the DBM bit set will 1856 clear the read-only bit (AP[2]) instead of raising a 1857 permission fault. 1858 1859 Kernels built with this configuration option enabled continue 1860 to work on pre-ARMv8.1 hardware and the performance impact is 1861 minimal. If unsure, say Y. 1862 1863config ARM64_PAN 1864 bool "Enable support for Privileged Access Never (PAN)" 1865 default y 1866 help 1867 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1868 prevents the kernel or hypervisor from accessing user-space (EL0) 1869 memory directly. 1870 1871 Choosing this option will cause any unprotected (not using 1872 copy_to_user et al) memory access to fail with a permission fault. 1873 1874 The feature is detected at runtime, and will remain as a 'nop' 1875 instruction if the cpu does not implement the feature. 1876 1877config ARM64_LSE_ATOMICS 1878 bool 1879 default ARM64_USE_LSE_ATOMICS 1880 1881config ARM64_USE_LSE_ATOMICS 1882 bool "Atomic instructions" 1883 default y 1884 help 1885 As part of the Large System Extensions, ARMv8.1 introduces new 1886 atomic instructions that are designed specifically to scale in 1887 very large systems. 1888 1889 Say Y here to make use of these instructions for the in-kernel 1890 atomic routines. This incurs a small overhead on CPUs that do 1891 not support these instructions. 1892 1893endmenu # "ARMv8.1 architectural features" 1894 1895menu "ARMv8.2 architectural features" 1896 1897config ARM64_PMEM 1898 bool "Enable support for persistent memory" 1899 select ARCH_HAS_PMEM_API 1900 select ARCH_HAS_UACCESS_FLUSHCACHE 1901 help 1902 Say Y to enable support for the persistent memory API based on the 1903 ARMv8.2 DCPoP feature. 1904 1905 The feature is detected at runtime, and the kernel will use DC CVAC 1906 operations if DC CVAP is not supported (following the behaviour of 1907 DC CVAP itself if the system does not define a point of persistence). 1908 1909config ARM64_RAS_EXTN 1910 bool "Enable support for RAS CPU Extensions" 1911 default y 1912 help 1913 CPUs that support the Reliability, Availability and Serviceability 1914 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1915 errors, classify them and report them to software. 1916 1917 On CPUs with these extensions system software can use additional 1918 barriers to determine if faults are pending and read the 1919 classification from a new set of registers. 1920 1921 Selecting this feature will allow the kernel to use these barriers 1922 and access the new registers if the system supports the extension. 1923 Platform RAS features may additionally depend on firmware support. 1924 1925config ARM64_CNP 1926 bool "Enable support for Common Not Private (CNP) translations" 1927 default y 1928 help 1929 Common Not Private (CNP) allows translation table entries to 1930 be shared between different PEs in the same inner shareable 1931 domain, so the hardware can use this fact to optimise the 1932 caching of such entries in the TLB. 1933 1934 Selecting this option allows the CNP feature to be detected 1935 at runtime, and does not affect PEs that do not implement 1936 this feature. 1937 1938endmenu # "ARMv8.2 architectural features" 1939 1940menu "ARMv8.3 architectural features" 1941 1942config ARM64_PTR_AUTH 1943 bool "Enable support for pointer authentication" 1944 default y 1945 help 1946 Pointer authentication (part of the ARMv8.3 Extensions) provides 1947 instructions for signing and authenticating pointers against secret 1948 keys, which can be used to mitigate Return Oriented Programming (ROP) 1949 and other attacks. 1950 1951 This option enables these instructions at EL0 (i.e. for userspace). 1952 Choosing this option will cause the kernel to initialise secret keys 1953 for each process at exec() time, with these keys being 1954 context-switched along with the process. 1955 1956 The feature is detected at runtime. If the feature is not present in 1957 hardware it will not be advertised to userspace/KVM guest nor will it 1958 be enabled. 1959 1960 If the feature is present on the boot CPU but not on a late CPU, then 1961 the late CPU will be parked. Also, if the boot CPU does not have 1962 address auth and the late CPU has then the late CPU will still boot 1963 but with the feature disabled. On such a system, this option should 1964 not be selected. 1965 1966config ARM64_PTR_AUTH_KERNEL 1967 bool "Use pointer authentication for kernel" 1968 default y 1969 depends on ARM64_PTR_AUTH 1970 # Modern compilers insert a .note.gnu.property section note for PAC 1971 # which is only understood by binutils starting with version 2.33.1. 1972 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1973 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1974 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1975 help 1976 If the compiler supports the -mbranch-protection or 1977 -msign-return-address flag (e.g. GCC 7 or later), then this option 1978 will cause the kernel itself to be compiled with return address 1979 protection. In this case, and if the target hardware is known to 1980 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1981 disabled with minimal loss of protection. 1982 1983 This feature works with FUNCTION_GRAPH_TRACER option only if 1984 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1985 1986config CC_HAS_BRANCH_PROT_PAC_RET 1987 # GCC 9 or later, clang 8 or later 1988 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1989 1990config AS_HAS_CFI_NEGATE_RA_STATE 1991 # binutils 2.34+ 1992 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1993 1994endmenu # "ARMv8.3 architectural features" 1995 1996menu "ARMv8.4 architectural features" 1997 1998config ARM64_AMU_EXTN 1999 bool "Enable support for the Activity Monitors Unit CPU extension" 2000 default y 2001 help 2002 The activity monitors extension is an optional extension introduced 2003 by the ARMv8.4 CPU architecture. This enables support for version 1 2004 of the activity monitors architecture, AMUv1. 2005 2006 To enable the use of this extension on CPUs that implement it, say Y. 2007 2008 Note that for architectural reasons, firmware _must_ implement AMU 2009 support when running on CPUs that present the activity monitors 2010 extension. The required support is present in: 2011 * Version 1.5 and later of the ARM Trusted Firmware 2012 2013 For kernels that have this configuration enabled but boot with broken 2014 firmware, you may need to say N here until the firmware is fixed. 2015 Otherwise you may experience firmware panics or lockups when 2016 accessing the counter registers. Even if you are not observing these 2017 symptoms, the values returned by the register reads might not 2018 correctly reflect reality. Most commonly, the value read will be 0, 2019 indicating that the counter is not enabled. 2020 2021config ARM64_TLB_RANGE 2022 bool "Enable support for tlbi range feature" 2023 default y 2024 help 2025 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2026 range of input addresses. 2027 2028endmenu # "ARMv8.4 architectural features" 2029 2030menu "ARMv8.5 architectural features" 2031 2032config AS_HAS_ARMV8_5 2033 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2034 2035config ARM64_BTI 2036 bool "Branch Target Identification support" 2037 default y 2038 help 2039 Branch Target Identification (part of the ARMv8.5 Extensions) 2040 provides a mechanism to limit the set of locations to which computed 2041 branch instructions such as BR or BLR can jump. 2042 2043 To make use of BTI on CPUs that support it, say Y. 2044 2045 BTI is intended to provide complementary protection to other control 2046 flow integrity protection mechanisms, such as the Pointer 2047 authentication mechanism provided as part of the ARMv8.3 Extensions. 2048 For this reason, it does not make sense to enable this option without 2049 also enabling support for pointer authentication. Thus, when 2050 enabling this option you should also select ARM64_PTR_AUTH=y. 2051 2052 Userspace binaries must also be specifically compiled to make use of 2053 this mechanism. If you say N here or the hardware does not support 2054 BTI, such binaries can still run, but you get no additional 2055 enforcement of branch destinations. 2056 2057config ARM64_BTI_KERNEL 2058 bool "Use Branch Target Identification for kernel" 2059 default y 2060 depends on ARM64_BTI 2061 depends on ARM64_PTR_AUTH_KERNEL 2062 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2063 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2064 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2065 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2066 depends on !CC_IS_GCC 2067 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2068 help 2069 Build the kernel with Branch Target Identification annotations 2070 and enable enforcement of this for kernel code. When this option 2071 is enabled and the system supports BTI all kernel code including 2072 modular code must have BTI enabled. 2073 2074config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2075 # GCC 9 or later, clang 8 or later 2076 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2077 2078config ARM64_E0PD 2079 bool "Enable support for E0PD" 2080 default y 2081 help 2082 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2083 that EL0 accesses made via TTBR1 always fault in constant time, 2084 providing similar benefits to KASLR as those provided by KPTI, but 2085 with lower overhead and without disrupting legitimate access to 2086 kernel memory such as SPE. 2087 2088 This option enables E0PD for TTBR1 where available. 2089 2090config ARM64_AS_HAS_MTE 2091 # Initial support for MTE went in binutils 2.32.0, checked with 2092 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2093 # as a late addition to the final architecture spec (LDGM/STGM) 2094 # is only supported in the newer 2.32.x and 2.33 binutils 2095 # versions, hence the extra "stgm" instruction check below. 2096 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2097 2098config ARM64_MTE 2099 bool "Memory Tagging Extension support" 2100 default y 2101 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2102 depends on AS_HAS_ARMV8_5 2103 # Required for tag checking in the uaccess routines 2104 select ARM64_PAN 2105 select ARCH_HAS_SUBPAGE_FAULTS 2106 select ARCH_USES_HIGH_VMA_FLAGS 2107 select ARCH_USES_PG_ARCH_2 2108 select ARCH_USES_PG_ARCH_3 2109 help 2110 Memory Tagging (part of the ARMv8.5 Extensions) provides 2111 architectural support for run-time, always-on detection of 2112 various classes of memory error to aid with software debugging 2113 to eliminate vulnerabilities arising from memory-unsafe 2114 languages. 2115 2116 This option enables the support for the Memory Tagging 2117 Extension at EL0 (i.e. for userspace). 2118 2119 Selecting this option allows the feature to be detected at 2120 runtime. Any secondary CPU not implementing this feature will 2121 not be allowed a late bring-up. 2122 2123 Userspace binaries that want to use this feature must 2124 explicitly opt in. The mechanism for the userspace is 2125 described in: 2126 2127 Documentation/arch/arm64/memory-tagging-extension.rst. 2128 2129endmenu # "ARMv8.5 architectural features" 2130 2131menu "ARMv8.7 architectural features" 2132 2133config ARM64_EPAN 2134 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2135 default y 2136 depends on ARM64_PAN 2137 help 2138 Enhanced Privileged Access Never (EPAN) allows Privileged 2139 Access Never to be used with Execute-only mappings. 2140 2141 The feature is detected at runtime, and will remain disabled 2142 if the cpu does not implement the feature. 2143endmenu # "ARMv8.7 architectural features" 2144 2145config AS_HAS_MOPS 2146 def_bool $(as-instr,.arch_extension mops) 2147 2148menu "ARMv8.9 architectural features" 2149 2150config ARM64_POE 2151 prompt "Permission Overlay Extension" 2152 def_bool y 2153 select ARCH_USES_HIGH_VMA_FLAGS 2154 select ARCH_HAS_PKEYS 2155 help 2156 The Permission Overlay Extension is used to implement Memory 2157 Protection Keys. Memory Protection Keys provides a mechanism for 2158 enforcing page-based protections, but without requiring modification 2159 of the page tables when an application changes protection domains. 2160 2161 For details, see Documentation/core-api/protection-keys.rst 2162 2163 If unsure, say y. 2164 2165config ARCH_PKEY_BITS 2166 int 2167 default 3 2168 2169config ARM64_HAFT 2170 bool "Support for Hardware managed Access Flag for Table Descriptors" 2171 depends on ARM64_HW_AFDBM 2172 default y 2173 help 2174 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2175 Flag for Table descriptors. When enabled an architectural executed 2176 memory access will update the Access Flag in each Table descriptor 2177 which is accessed during the translation table walk and for which 2178 the Access Flag is 0. The Access Flag of the Table descriptor use 2179 the same bit of PTE_AF. 2180 2181 The feature will only be enabled if all the CPUs in the system 2182 support this feature. If unsure, say Y. 2183 2184endmenu # "ARMv8.9 architectural features" 2185 2186menu "ARMv9.4 architectural features" 2187 2188config ARM64_GCS 2189 bool "Enable support for Guarded Control Stack (GCS)" 2190 default y 2191 select ARCH_HAS_USER_SHADOW_STACK 2192 select ARCH_USES_HIGH_VMA_FLAGS 2193 help 2194 Guarded Control Stack (GCS) provides support for a separate 2195 stack with restricted access which contains only return 2196 addresses. This can be used to harden against some attacks 2197 by comparing return address used by the program with what is 2198 stored in the GCS, and may also be used to efficiently obtain 2199 the call stack for applications such as profiling. 2200 2201 The feature is detected at runtime, and will remain disabled 2202 if the system does not implement the feature. 2203 2204endmenu # "ARMv9.4 architectural features" 2205 2206config ARM64_SVE 2207 bool "ARM Scalable Vector Extension support" 2208 default y 2209 help 2210 The Scalable Vector Extension (SVE) is an extension to the AArch64 2211 execution state which complements and extends the SIMD functionality 2212 of the base architecture to support much larger vectors and to enable 2213 additional vectorisation opportunities. 2214 2215 To enable use of this extension on CPUs that implement it, say Y. 2216 2217 On CPUs that support the SVE2 extensions, this option will enable 2218 those too. 2219 2220 Note that for architectural reasons, firmware _must_ implement SVE 2221 support when running on SVE capable hardware. The required support 2222 is present in: 2223 2224 * version 1.5 and later of the ARM Trusted Firmware 2225 * the AArch64 boot wrapper since commit 5e1261e08abf 2226 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2227 2228 For other firmware implementations, consult the firmware documentation 2229 or vendor. 2230 2231 If you need the kernel to boot on SVE-capable hardware with broken 2232 firmware, you may need to say N here until you get your firmware 2233 fixed. Otherwise, you may experience firmware panics or lockups when 2234 booting the kernel. If unsure and you are not observing these 2235 symptoms, you should assume that it is safe to say Y. 2236 2237config ARM64_SME 2238 bool "ARM Scalable Matrix Extension support" 2239 default y 2240 depends on ARM64_SVE 2241 help 2242 The Scalable Matrix Extension (SME) is an extension to the AArch64 2243 execution state which utilises a substantial subset of the SVE 2244 instruction set, together with the addition of new architectural 2245 register state capable of holding two dimensional matrix tiles to 2246 enable various matrix operations. 2247 2248config ARM64_PSEUDO_NMI 2249 bool "Support for NMI-like interrupts" 2250 select ARM_GIC_V3 2251 help 2252 Adds support for mimicking Non-Maskable Interrupts through the use of 2253 GIC interrupt priority. This support requires version 3 or later of 2254 ARM GIC. 2255 2256 This high priority configuration for interrupts needs to be 2257 explicitly enabled by setting the kernel parameter 2258 "irqchip.gicv3_pseudo_nmi" to 1. 2259 2260 If unsure, say N 2261 2262if ARM64_PSEUDO_NMI 2263config ARM64_DEBUG_PRIORITY_MASKING 2264 bool "Debug interrupt priority masking" 2265 help 2266 This adds runtime checks to functions enabling/disabling 2267 interrupts when using priority masking. The additional checks verify 2268 the validity of ICC_PMR_EL1 when calling concerned functions. 2269 2270 If unsure, say N 2271endif # ARM64_PSEUDO_NMI 2272 2273config RELOCATABLE 2274 bool "Build a relocatable kernel image" if EXPERT 2275 select ARCH_HAS_RELR 2276 default y 2277 help 2278 This builds the kernel as a Position Independent Executable (PIE), 2279 which retains all relocation metadata required to relocate the 2280 kernel binary at runtime to a different virtual address than the 2281 address it was linked at. 2282 Since AArch64 uses the RELA relocation format, this requires a 2283 relocation pass at runtime even if the kernel is loaded at the 2284 same address it was linked at. 2285 2286config RANDOMIZE_BASE 2287 bool "Randomize the address of the kernel image" 2288 select RELOCATABLE 2289 help 2290 Randomizes the virtual address at which the kernel image is 2291 loaded, as a security feature that deters exploit attempts 2292 relying on knowledge of the location of kernel internals. 2293 2294 It is the bootloader's job to provide entropy, by passing a 2295 random u64 value in /chosen/kaslr-seed at kernel entry. 2296 2297 When booting via the UEFI stub, it will invoke the firmware's 2298 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2299 to the kernel proper. In addition, it will randomise the physical 2300 location of the kernel Image as well. 2301 2302 If unsure, say N. 2303 2304config RANDOMIZE_MODULE_REGION_FULL 2305 bool "Randomize the module region over a 2 GB range" 2306 depends on RANDOMIZE_BASE 2307 default y 2308 help 2309 Randomizes the location of the module region inside a 2 GB window 2310 covering the core kernel. This way, it is less likely for modules 2311 to leak information about the location of core kernel data structures 2312 but it does imply that function calls between modules and the core 2313 kernel will need to be resolved via veneers in the module PLT. 2314 2315 When this option is not set, the module region will be randomized over 2316 a limited range that contains the [_stext, _etext] interval of the 2317 core kernel, so branch relocations are almost always in range unless 2318 the region is exhausted. In this particular case of region 2319 exhaustion, modules might be able to fall back to a larger 2GB area. 2320 2321config CC_HAVE_STACKPROTECTOR_SYSREG 2322 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2323 2324config STACKPROTECTOR_PER_TASK 2325 def_bool y 2326 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2327 2328config UNWIND_PATCH_PAC_INTO_SCS 2329 bool "Enable shadow call stack dynamically using code patching" 2330 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2331 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2332 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2333 depends on SHADOW_CALL_STACK 2334 select UNWIND_TABLES 2335 select DYNAMIC_SCS 2336 2337config ARM64_CONTPTE 2338 bool "Contiguous PTE mappings for user memory" if EXPERT 2339 depends on TRANSPARENT_HUGEPAGE 2340 default y 2341 help 2342 When enabled, user mappings are configured using the PTE contiguous 2343 bit, for any mappings that meet the size and alignment requirements. 2344 This reduces TLB pressure and improves performance. 2345 2346endmenu # "Kernel Features" 2347 2348menu "Boot options" 2349 2350config ARM64_ACPI_PARKING_PROTOCOL 2351 bool "Enable support for the ARM64 ACPI parking protocol" 2352 depends on ACPI 2353 help 2354 Enable support for the ARM64 ACPI parking protocol. If disabled 2355 the kernel will not allow booting through the ARM64 ACPI parking 2356 protocol even if the corresponding data is present in the ACPI 2357 MADT table. 2358 2359config CMDLINE 2360 string "Default kernel command string" 2361 default "" 2362 help 2363 Provide a set of default command-line options at build time by 2364 entering them here. As a minimum, you should specify the the 2365 root device (e.g. root=/dev/nfs). 2366 2367choice 2368 prompt "Kernel command line type" 2369 depends on CMDLINE != "" 2370 default CMDLINE_FROM_BOOTLOADER 2371 help 2372 Choose how the kernel will handle the provided default kernel 2373 command line string. 2374 2375config CMDLINE_FROM_BOOTLOADER 2376 bool "Use bootloader kernel arguments if available" 2377 help 2378 Uses the command-line options passed by the boot loader. If 2379 the boot loader doesn't provide any, the default kernel command 2380 string provided in CMDLINE will be used. 2381 2382config CMDLINE_FORCE 2383 bool "Always use the default kernel command string" 2384 help 2385 Always use the default kernel command string, even if the boot 2386 loader passes other arguments to the kernel. 2387 This is useful if you cannot or don't want to change the 2388 command-line options your boot loader passes to the kernel. 2389 2390endchoice 2391 2392config EFI_STUB 2393 bool 2394 2395config EFI 2396 bool "UEFI runtime support" 2397 depends on OF && !CPU_BIG_ENDIAN 2398 depends on KERNEL_MODE_NEON 2399 select ARCH_SUPPORTS_ACPI 2400 select LIBFDT 2401 select UCS2_STRING 2402 select EFI_PARAMS_FROM_FDT 2403 select EFI_RUNTIME_WRAPPERS 2404 select EFI_STUB 2405 select EFI_GENERIC_STUB 2406 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2407 default y 2408 help 2409 This option provides support for runtime services provided 2410 by UEFI firmware (such as non-volatile variables, realtime 2411 clock, and platform reset). A UEFI stub is also provided to 2412 allow the kernel to be booted as an EFI application. This 2413 is only useful on systems that have UEFI firmware. 2414 2415config COMPRESSED_INSTALL 2416 bool "Install compressed image by default" 2417 help 2418 This makes the regular "make install" install the compressed 2419 image we built, not the legacy uncompressed one. 2420 2421 You can check that a compressed image works for you by doing 2422 "make zinstall" first, and verifying that everything is fine 2423 in your environment before making "make install" do this for 2424 you. 2425 2426config DMI 2427 bool "Enable support for SMBIOS (DMI) tables" 2428 depends on EFI 2429 default y 2430 help 2431 This enables SMBIOS/DMI feature for systems. 2432 2433 This option is only useful on systems that have UEFI firmware. 2434 However, even with this option, the resultant kernel should 2435 continue to boot on existing non-UEFI platforms. 2436 2437endmenu # "Boot options" 2438 2439menu "Power management options" 2440 2441source "kernel/power/Kconfig" 2442 2443config ARCH_HIBERNATION_POSSIBLE 2444 def_bool y 2445 depends on CPU_PM 2446 2447config ARCH_HIBERNATION_HEADER 2448 def_bool y 2449 depends on HIBERNATION 2450 2451config ARCH_SUSPEND_POSSIBLE 2452 def_bool y 2453 2454endmenu # "Power management options" 2455 2456menu "CPU Power Management" 2457 2458source "drivers/cpuidle/Kconfig" 2459 2460source "drivers/cpufreq/Kconfig" 2461 2462endmenu # "CPU Power Management" 2463 2464source "drivers/acpi/Kconfig" 2465 2466source "arch/arm64/kvm/Kconfig" 2467 2468source "kernel/livepatch/Kconfig" 2469