1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CRC32 25 select ARCH_HAS_CRC_T10DIF if KERNEL_MODE_NEON 26 select ARCH_HAS_CURRENT_STACK_POINTER 27 select ARCH_HAS_DEBUG_VIRTUAL 28 select ARCH_HAS_DEBUG_VM_PGTABLE 29 select ARCH_HAS_DMA_OPS if XEN 30 select ARCH_HAS_DMA_PREP_COHERENT 31 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 32 select ARCH_HAS_FAST_MULTIPLIER 33 select ARCH_HAS_FORTIFY_SOURCE 34 select ARCH_HAS_GCOV_PROFILE_ALL 35 select ARCH_HAS_GIGANTIC_PAGE 36 select ARCH_HAS_KCOV 37 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 38 select ARCH_HAS_KEEPINITRD 39 select ARCH_HAS_MEMBARRIER_SYNC_CORE 40 select ARCH_HAS_MEM_ENCRYPT 41 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 42 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 43 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 44 select ARCH_HAS_PTE_DEVMAP 45 select ARCH_HAS_PTE_SPECIAL 46 select ARCH_HAS_HW_PTE_YOUNG 47 select ARCH_HAS_SETUP_DMA_OPS 48 select ARCH_HAS_SET_DIRECT_MAP 49 select ARCH_HAS_SET_MEMORY 50 select ARCH_HAS_MEM_ENCRYPT 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_SYSCALL_WRAPPER 58 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 59 select ARCH_HAS_ZONE_DMA_SET if EXPERT 60 select ARCH_HAVE_ELF_PROT 61 select ARCH_HAVE_NMI_SAFE_CMPXCHG 62 select ARCH_HAVE_TRACE_MMIO_ACCESS 63 select ARCH_INLINE_READ_LOCK if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 65 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 70 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 73 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 74 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 77 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 78 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 79 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 83 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 84 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 87 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 88 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 89 select ARCH_KEEP_MEMBLOCK 90 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 91 select ARCH_USE_CMPXCHG_LOCKREF 92 select ARCH_USE_GNU_PROPERTY 93 select ARCH_USE_MEMTEST 94 select ARCH_USE_QUEUED_RWLOCKS 95 select ARCH_USE_QUEUED_SPINLOCKS 96 select ARCH_USE_SYM_ANNOTATIONS 97 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 98 select ARCH_SUPPORTS_HUGETLBFS 99 select ARCH_SUPPORTS_MEMORY_FAILURE 100 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 101 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 102 select ARCH_SUPPORTS_LTO_CLANG_THIN 103 select ARCH_SUPPORTS_CFI_CLANG 104 select ARCH_SUPPORTS_ATOMIC_RMW 105 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 106 select ARCH_SUPPORTS_NUMA_BALANCING 107 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 108 select ARCH_SUPPORTS_PER_VMA_LOCK 109 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 110 select ARCH_SUPPORTS_RT 111 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 112 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 113 select ARCH_WANT_DEFAULT_BPF_JIT 114 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 115 select ARCH_WANT_FRAME_POINTERS 116 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 117 select ARCH_WANT_LD_ORPHAN_WARN 118 select ARCH_WANTS_EXECMEM_LATE 119 select ARCH_WANTS_NO_INSTR 120 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 121 select ARCH_HAS_UBSAN 122 select ARM_AMBA 123 select ARM_ARCH_TIMER 124 select ARM_GIC 125 select AUDIT_ARCH_COMPAT_GENERIC 126 select ARM_GIC_V2M if PCI 127 select ARM_GIC_V3 128 select ARM_GIC_V3_ITS if PCI 129 select ARM_PSCI_FW 130 select BUILDTIME_TABLE_SORT 131 select CLONE_BACKWARDS 132 select COMMON_CLK 133 select CPU_PM if (SUSPEND || CPU_IDLE) 134 select CPUMASK_OFFSTACK if NR_CPUS > 256 135 select CRC32 136 select DCACHE_WORD_ACCESS 137 select DYNAMIC_FTRACE if FUNCTION_TRACER 138 select DMA_BOUNCE_UNALIGNED_KMALLOC 139 select DMA_DIRECT_REMAP 140 select EDAC_SUPPORT 141 select FRAME_POINTER 142 select FUNCTION_ALIGNMENT_4B 143 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 144 select GENERIC_ALLOCATOR 145 select GENERIC_ARCH_TOPOLOGY 146 select GENERIC_CLOCKEVENTS_BROADCAST 147 select GENERIC_CPU_AUTOPROBE 148 select GENERIC_CPU_DEVICES 149 select GENERIC_CPU_VULNERABILITIES 150 select GENERIC_EARLY_IOREMAP 151 select GENERIC_IDLE_POLL_SETUP 152 select GENERIC_IOREMAP 153 select GENERIC_IRQ_IPI 154 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 155 select GENERIC_IRQ_PROBE 156 select GENERIC_IRQ_SHOW 157 select GENERIC_IRQ_SHOW_LEVEL 158 select GENERIC_LIB_DEVMEM_IS_ALLOWED 159 select GENERIC_PCI_IOMAP 160 select GENERIC_PTDUMP 161 select GENERIC_SCHED_CLOCK 162 select GENERIC_SMP_IDLE_THREAD 163 select GENERIC_TIME_VSYSCALL 164 select GENERIC_GETTIMEOFDAY 165 select GENERIC_VDSO_TIME_NS 166 select HARDIRQS_SW_RESEND 167 select HAS_IOPORT 168 select HAVE_MOVE_PMD 169 select HAVE_MOVE_PUD 170 select HAVE_PCI 171 select HAVE_ACPI_APEI if (ACPI && EFI) 172 select HAVE_ALIGNED_STRUCT_PAGE 173 select HAVE_ARCH_AUDITSYSCALL 174 select HAVE_ARCH_BITREVERSE 175 select HAVE_ARCH_COMPILER_H 176 select HAVE_ARCH_HUGE_VMALLOC 177 select HAVE_ARCH_HUGE_VMAP 178 select HAVE_ARCH_JUMP_LABEL 179 select HAVE_ARCH_JUMP_LABEL_RELATIVE 180 select HAVE_ARCH_KASAN 181 select HAVE_ARCH_KASAN_VMALLOC 182 select HAVE_ARCH_KASAN_SW_TAGS 183 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 184 # Some instrumentation may be unsound, hence EXPERT 185 select HAVE_ARCH_KCSAN if EXPERT 186 select HAVE_ARCH_KFENCE 187 select HAVE_ARCH_KGDB 188 select HAVE_ARCH_MMAP_RND_BITS 189 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 190 select HAVE_ARCH_PREL32_RELOCATIONS 191 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 192 select HAVE_ARCH_SECCOMP_FILTER 193 select HAVE_ARCH_STACKLEAK 194 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 195 select HAVE_ARCH_TRACEHOOK 196 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 197 select HAVE_ARCH_VMAP_STACK 198 select HAVE_ARM_SMCCC 199 select HAVE_ASM_MODVERSIONS 200 select HAVE_EBPF_JIT 201 select HAVE_C_RECORDMCOUNT 202 select HAVE_CMPXCHG_DOUBLE 203 select HAVE_CMPXCHG_LOCAL 204 select HAVE_CONTEXT_TRACKING_USER 205 select HAVE_DEBUG_KMEMLEAK 206 select HAVE_DMA_CONTIGUOUS 207 select HAVE_DYNAMIC_FTRACE 208 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 209 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 210 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 211 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 212 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 213 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 214 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 215 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 216 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 217 if DYNAMIC_FTRACE_WITH_ARGS 218 select HAVE_SAMPLE_FTRACE_DIRECT 219 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 220 select HAVE_EFFICIENT_UNALIGNED_ACCESS 221 select HAVE_GUP_FAST 222 select HAVE_FTRACE_GRAPH_FUNC 223 select HAVE_FTRACE_MCOUNT_RECORD 224 select HAVE_FUNCTION_TRACER 225 select HAVE_FUNCTION_ERROR_INJECTION 226 select HAVE_FUNCTION_GRAPH_FREGS 227 select HAVE_FUNCTION_GRAPH_TRACER 228 select HAVE_FUNCTION_GRAPH_RETVAL 229 select HAVE_GCC_PLUGINS 230 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 231 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 232 select HAVE_HW_BREAKPOINT if PERF_EVENTS 233 select HAVE_IOREMAP_PROT 234 select HAVE_IRQ_TIME_ACCOUNTING 235 select HAVE_MOD_ARCH_SPECIFIC 236 select HAVE_NMI 237 select HAVE_PERF_EVENTS 238 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 239 select HAVE_PERF_REGS 240 select HAVE_PERF_USER_STACK_DUMP 241 select HAVE_PREEMPT_DYNAMIC_KEY 242 select HAVE_REGS_AND_STACK_ACCESS_API 243 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 244 select HAVE_FUNCTION_ARG_ACCESS_API 245 select MMU_GATHER_RCU_TABLE_FREE 246 select HAVE_RSEQ 247 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 248 select HAVE_STACKPROTECTOR 249 select HAVE_SYSCALL_TRACEPOINTS 250 select HAVE_KPROBES 251 select HAVE_KRETPROBES 252 select HAVE_GENERIC_VDSO 253 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 254 select IRQ_DOMAIN 255 select IRQ_FORCED_THREADING 256 select KASAN_VMALLOC if KASAN 257 select LOCK_MM_AND_FIND_VMA 258 select MODULES_USE_ELF_RELA 259 select NEED_DMA_MAP_STATE 260 select NEED_SG_DMA_LENGTH 261 select OF 262 select OF_EARLY_FLATTREE 263 select PCI_DOMAINS_GENERIC if PCI 264 select PCI_ECAM if (ACPI && PCI) 265 select PCI_SYSCALL if PCI 266 select POWER_RESET 267 select POWER_SUPPLY 268 select SPARSE_IRQ 269 select SWIOTLB 270 select SYSCTL_EXCEPTION_TRACE 271 select THREAD_INFO_IN_TASK 272 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 273 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 274 select TRACE_IRQFLAGS_SUPPORT 275 select TRACE_IRQFLAGS_NMI_SUPPORT 276 select HAVE_SOFTIRQ_ON_OWN_STACK 277 select USER_STACKTRACE_SUPPORT 278 select VDSO_GETRANDOM 279 help 280 ARM 64-bit (AArch64) Linux support. 281 282config RUSTC_SUPPORTS_ARM64 283 def_bool y 284 depends on CPU_LITTLE_ENDIAN 285 # Shadow call stack is only supported on certain rustc versions. 286 # 287 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 288 # required due to use of the -Zfixed-x18 flag. 289 # 290 # Otherwise, rustc version 1.82+ is required due to use of the 291 # -Zsanitizer=shadow-call-stack flag. 292 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 293 294config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 295 def_bool CC_IS_CLANG 296 # https://github.com/ClangBuiltLinux/linux/issues/1507 297 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 298 299config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 300 def_bool CC_IS_GCC 301 depends on $(cc-option,-fpatchable-function-entry=2) 302 303config 64BIT 304 def_bool y 305 306config MMU 307 def_bool y 308 309config ARM64_CONT_PTE_SHIFT 310 int 311 default 5 if PAGE_SIZE_64KB 312 default 7 if PAGE_SIZE_16KB 313 default 4 314 315config ARM64_CONT_PMD_SHIFT 316 int 317 default 5 if PAGE_SIZE_64KB 318 default 5 if PAGE_SIZE_16KB 319 default 4 320 321config ARCH_MMAP_RND_BITS_MIN 322 default 14 if PAGE_SIZE_64KB 323 default 16 if PAGE_SIZE_16KB 324 default 18 325 326# max bits determined by the following formula: 327# VA_BITS - PAGE_SHIFT - 3 328config ARCH_MMAP_RND_BITS_MAX 329 default 19 if ARM64_VA_BITS=36 330 default 24 if ARM64_VA_BITS=39 331 default 27 if ARM64_VA_BITS=42 332 default 30 if ARM64_VA_BITS=47 333 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 334 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 335 default 33 if ARM64_VA_BITS=48 336 default 14 if ARM64_64K_PAGES 337 default 16 if ARM64_16K_PAGES 338 default 18 339 340config ARCH_MMAP_RND_COMPAT_BITS_MIN 341 default 7 if ARM64_64K_PAGES 342 default 9 if ARM64_16K_PAGES 343 default 11 344 345config ARCH_MMAP_RND_COMPAT_BITS_MAX 346 default 16 347 348config NO_IOPORT_MAP 349 def_bool y if !PCI 350 351config STACKTRACE_SUPPORT 352 def_bool y 353 354config ILLEGAL_POINTER_VALUE 355 hex 356 default 0xdead000000000000 357 358config LOCKDEP_SUPPORT 359 def_bool y 360 361config GENERIC_BUG 362 def_bool y 363 depends on BUG 364 365config GENERIC_BUG_RELATIVE_POINTERS 366 def_bool y 367 depends on GENERIC_BUG 368 369config GENERIC_HWEIGHT 370 def_bool y 371 372config GENERIC_CSUM 373 def_bool y 374 375config GENERIC_CALIBRATE_DELAY 376 def_bool y 377 378config SMP 379 def_bool y 380 381config KERNEL_MODE_NEON 382 def_bool y 383 384config FIX_EARLYCON_MEM 385 def_bool y 386 387config PGTABLE_LEVELS 388 int 389 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 390 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 391 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 392 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 393 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 394 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 395 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 396 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 397 398config ARCH_SUPPORTS_UPROBES 399 def_bool y 400 401config ARCH_PROC_KCORE_TEXT 402 def_bool y 403 404config BROKEN_GAS_INST 405 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 406 407config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 408 bool 409 # Clang's __builtin_return_address() strips the PAC since 12.0.0 410 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 411 default y if CC_IS_CLANG 412 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 413 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 414 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 415 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 416 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 417 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 418 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 419 default n 420 421config KASAN_SHADOW_OFFSET 422 hex 423 depends on KASAN_GENERIC || KASAN_SW_TAGS 424 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 425 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 426 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 427 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 428 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 429 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 430 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 431 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 432 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 433 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 434 default 0xffffffffffffffff 435 436config UNWIND_TABLES 437 bool 438 439source "arch/arm64/Kconfig.platforms" 440 441menu "Kernel Features" 442 443menu "ARM errata workarounds via the alternatives framework" 444 445config AMPERE_ERRATUM_AC03_CPU_38 446 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 447 default y 448 help 449 This option adds an alternative code sequence to work around Ampere 450 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 451 452 The affected design reports FEAT_HAFDBS as not implemented in 453 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 454 as required by the architecture. The unadvertised HAFDBS 455 implementation suffers from an additional erratum where hardware 456 A/D updates can occur after a PTE has been marked invalid. 457 458 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 459 which avoids enabling unadvertised hardware Access Flag management 460 at stage-2. 461 462 If unsure, say Y. 463 464config ARM64_WORKAROUND_CLEAN_CACHE 465 bool 466 467config ARM64_ERRATUM_826319 468 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 469 default y 470 select ARM64_WORKAROUND_CLEAN_CACHE 471 help 472 This option adds an alternative code sequence to work around ARM 473 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 474 AXI master interface and an L2 cache. 475 476 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 477 and is unable to accept a certain write via this interface, it will 478 not progress on read data presented on the read data channel and the 479 system can deadlock. 480 481 The workaround promotes data cache clean instructions to 482 data cache clean-and-invalidate. 483 Please note that this does not necessarily enable the workaround, 484 as it depends on the alternative framework, which will only patch 485 the kernel if an affected CPU is detected. 486 487 If unsure, say Y. 488 489config ARM64_ERRATUM_827319 490 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 491 default y 492 select ARM64_WORKAROUND_CLEAN_CACHE 493 help 494 This option adds an alternative code sequence to work around ARM 495 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 496 master interface and an L2 cache. 497 498 Under certain conditions this erratum can cause a clean line eviction 499 to occur at the same time as another transaction to the same address 500 on the AMBA 5 CHI interface, which can cause data corruption if the 501 interconnect reorders the two transactions. 502 503 The workaround promotes data cache clean instructions to 504 data cache clean-and-invalidate. 505 Please note that this does not necessarily enable the workaround, 506 as it depends on the alternative framework, which will only patch 507 the kernel if an affected CPU is detected. 508 509 If unsure, say Y. 510 511config ARM64_ERRATUM_824069 512 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 513 default y 514 select ARM64_WORKAROUND_CLEAN_CACHE 515 help 516 This option adds an alternative code sequence to work around ARM 517 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 518 to a coherent interconnect. 519 520 If a Cortex-A53 processor is executing a store or prefetch for 521 write instruction at the same time as a processor in another 522 cluster is executing a cache maintenance operation to the same 523 address, then this erratum might cause a clean cache line to be 524 incorrectly marked as dirty. 525 526 The workaround promotes data cache clean instructions to 527 data cache clean-and-invalidate. 528 Please note that this option does not necessarily enable the 529 workaround, as it depends on the alternative framework, which will 530 only patch the kernel if an affected CPU is detected. 531 532 If unsure, say Y. 533 534config ARM64_ERRATUM_819472 535 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 536 default y 537 select ARM64_WORKAROUND_CLEAN_CACHE 538 help 539 This option adds an alternative code sequence to work around ARM 540 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 541 present when it is connected to a coherent interconnect. 542 543 If the processor is executing a load and store exclusive sequence at 544 the same time as a processor in another cluster is executing a cache 545 maintenance operation to the same address, then this erratum might 546 cause data corruption. 547 548 The workaround promotes data cache clean instructions to 549 data cache clean-and-invalidate. 550 Please note that this does not necessarily enable the workaround, 551 as it depends on the alternative framework, which will only patch 552 the kernel if an affected CPU is detected. 553 554 If unsure, say Y. 555 556config ARM64_ERRATUM_832075 557 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 558 default y 559 help 560 This option adds an alternative code sequence to work around ARM 561 erratum 832075 on Cortex-A57 parts up to r1p2. 562 563 Affected Cortex-A57 parts might deadlock when exclusive load/store 564 instructions to Write-Back memory are mixed with Device loads. 565 566 The workaround is to promote device loads to use Load-Acquire 567 semantics. 568 Please note that this does not necessarily enable the workaround, 569 as it depends on the alternative framework, which will only patch 570 the kernel if an affected CPU is detected. 571 572 If unsure, say Y. 573 574config ARM64_ERRATUM_834220 575 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 576 depends on KVM 577 help 578 This option adds an alternative code sequence to work around ARM 579 erratum 834220 on Cortex-A57 parts up to r1p2. 580 581 Affected Cortex-A57 parts might report a Stage 2 translation 582 fault as the result of a Stage 1 fault for load crossing a 583 page boundary when there is a permission or device memory 584 alignment fault at Stage 1 and a translation fault at Stage 2. 585 586 The workaround is to verify that the Stage 1 translation 587 doesn't generate a fault before handling the Stage 2 fault. 588 Please note that this does not necessarily enable the workaround, 589 as it depends on the alternative framework, which will only patch 590 the kernel if an affected CPU is detected. 591 592 If unsure, say N. 593 594config ARM64_ERRATUM_1742098 595 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 596 depends on COMPAT 597 default y 598 help 599 This option removes the AES hwcap for aarch32 user-space to 600 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 601 602 Affected parts may corrupt the AES state if an interrupt is 603 taken between a pair of AES instructions. These instructions 604 are only present if the cryptography extensions are present. 605 All software should have a fallback implementation for CPUs 606 that don't implement the cryptography extensions. 607 608 If unsure, say Y. 609 610config ARM64_ERRATUM_845719 611 bool "Cortex-A53: 845719: a load might read incorrect data" 612 depends on COMPAT 613 default y 614 help 615 This option adds an alternative code sequence to work around ARM 616 erratum 845719 on Cortex-A53 parts up to r0p4. 617 618 When running a compat (AArch32) userspace on an affected Cortex-A53 619 part, a load at EL0 from a virtual address that matches the bottom 32 620 bits of the virtual address used by a recent load at (AArch64) EL1 621 might return incorrect data. 622 623 The workaround is to write the contextidr_el1 register on exception 624 return to a 32-bit task. 625 Please note that this does not necessarily enable the workaround, 626 as it depends on the alternative framework, which will only patch 627 the kernel if an affected CPU is detected. 628 629 If unsure, say Y. 630 631config ARM64_ERRATUM_843419 632 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 633 default y 634 help 635 This option links the kernel with '--fix-cortex-a53-843419' and 636 enables PLT support to replace certain ADRP instructions, which can 637 cause subsequent memory accesses to use an incorrect address on 638 Cortex-A53 parts up to r0p4. 639 640 If unsure, say Y. 641 642config ARM64_LD_HAS_FIX_ERRATUM_843419 643 def_bool $(ld-option,--fix-cortex-a53-843419) 644 645config ARM64_ERRATUM_1024718 646 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 647 default y 648 help 649 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 650 651 Affected Cortex-A55 cores (all revisions) could cause incorrect 652 update of the hardware dirty bit when the DBM/AP bits are updated 653 without a break-before-make. The workaround is to disable the usage 654 of hardware DBM locally on the affected cores. CPUs not affected by 655 this erratum will continue to use the feature. 656 657 If unsure, say Y. 658 659config ARM64_ERRATUM_1418040 660 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 661 default y 662 depends on COMPAT 663 help 664 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 665 errata 1188873 and 1418040. 666 667 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 668 cause register corruption when accessing the timer registers 669 from AArch32 userspace. 670 671 If unsure, say Y. 672 673config ARM64_WORKAROUND_SPECULATIVE_AT 674 bool 675 676config ARM64_ERRATUM_1165522 677 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 678 default y 679 select ARM64_WORKAROUND_SPECULATIVE_AT 680 help 681 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 682 683 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 684 corrupted TLBs by speculating an AT instruction during a guest 685 context switch. 686 687 If unsure, say Y. 688 689config ARM64_ERRATUM_1319367 690 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 691 default y 692 select ARM64_WORKAROUND_SPECULATIVE_AT 693 help 694 This option adds work arounds for ARM Cortex-A57 erratum 1319537 695 and A72 erratum 1319367 696 697 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 698 speculating an AT instruction during a guest context switch. 699 700 If unsure, say Y. 701 702config ARM64_ERRATUM_1530923 703 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 704 default y 705 select ARM64_WORKAROUND_SPECULATIVE_AT 706 help 707 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 708 709 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 710 corrupted TLBs by speculating an AT instruction during a guest 711 context switch. 712 713 If unsure, say Y. 714 715config ARM64_WORKAROUND_REPEAT_TLBI 716 bool 717 718config ARM64_ERRATUM_2441007 719 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 720 select ARM64_WORKAROUND_REPEAT_TLBI 721 help 722 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 723 724 Under very rare circumstances, affected Cortex-A55 CPUs 725 may not handle a race between a break-before-make sequence on one 726 CPU, and another CPU accessing the same page. This could allow a 727 store to a page that has been unmapped. 728 729 Work around this by adding the affected CPUs to the list that needs 730 TLB sequences to be done twice. 731 732 If unsure, say N. 733 734config ARM64_ERRATUM_1286807 735 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 736 select ARM64_WORKAROUND_REPEAT_TLBI 737 help 738 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 739 740 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 741 address for a cacheable mapping of a location is being 742 accessed by a core while another core is remapping the virtual 743 address to a new physical page using the recommended 744 break-before-make sequence, then under very rare circumstances 745 TLBI+DSB completes before a read using the translation being 746 invalidated has been observed by other observers. The 747 workaround repeats the TLBI+DSB operation. 748 749 If unsure, say N. 750 751config ARM64_ERRATUM_1463225 752 bool "Cortex-A76: Software Step might prevent interrupt recognition" 753 default y 754 help 755 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 756 757 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 758 of a system call instruction (SVC) can prevent recognition of 759 subsequent interrupts when software stepping is disabled in the 760 exception handler of the system call and either kernel debugging 761 is enabled or VHE is in use. 762 763 Work around the erratum by triggering a dummy step exception 764 when handling a system call from a task that is being stepped 765 in a VHE configuration of the kernel. 766 767 If unsure, say Y. 768 769config ARM64_ERRATUM_1542419 770 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 771 help 772 This option adds a workaround for ARM Neoverse-N1 erratum 773 1542419. 774 775 Affected Neoverse-N1 cores could execute a stale instruction when 776 modified by another CPU. The workaround depends on a firmware 777 counterpart. 778 779 Workaround the issue by hiding the DIC feature from EL0. This 780 forces user-space to perform cache maintenance. 781 782 If unsure, say N. 783 784config ARM64_ERRATUM_1508412 785 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 786 default y 787 help 788 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 789 790 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 791 of a store-exclusive or read of PAR_EL1 and a load with device or 792 non-cacheable memory attributes. The workaround depends on a firmware 793 counterpart. 794 795 KVM guests must also have the workaround implemented or they can 796 deadlock the system. 797 798 Work around the issue by inserting DMB SY barriers around PAR_EL1 799 register reads and warning KVM users. The DMB barrier is sufficient 800 to prevent a speculative PAR_EL1 read. 801 802 If unsure, say Y. 803 804config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 805 bool 806 807config ARM64_ERRATUM_2051678 808 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 809 default y 810 help 811 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 812 Affected Cortex-A510 might not respect the ordering rules for 813 hardware update of the page table's dirty bit. The workaround 814 is to not enable the feature on affected CPUs. 815 816 If unsure, say Y. 817 818config ARM64_ERRATUM_2077057 819 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 820 default y 821 help 822 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 823 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 824 expected, but a Pointer Authentication trap is taken instead. The 825 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 826 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 827 828 This can only happen when EL2 is stepping EL1. 829 830 When these conditions occur, the SPSR_EL2 value is unchanged from the 831 previous guest entry, and can be restored from the in-memory copy. 832 833 If unsure, say Y. 834 835config ARM64_ERRATUM_2658417 836 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 837 default y 838 help 839 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 840 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 841 BFMMLA or VMMLA instructions in rare circumstances when a pair of 842 A510 CPUs are using shared neon hardware. As the sharing is not 843 discoverable by the kernel, hide the BF16 HWCAP to indicate that 844 user-space should not be using these instructions. 845 846 If unsure, say Y. 847 848config ARM64_ERRATUM_2119858 849 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 850 default y 851 depends on CORESIGHT_TRBE 852 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 853 help 854 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 855 856 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 857 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 858 the event of a WRAP event. 859 860 Work around the issue by always making sure we move the TRBPTR_EL1 by 861 256 bytes before enabling the buffer and filling the first 256 bytes of 862 the buffer with ETM ignore packets upon disabling. 863 864 If unsure, say Y. 865 866config ARM64_ERRATUM_2139208 867 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 868 default y 869 depends on CORESIGHT_TRBE 870 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 871 help 872 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 873 874 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 875 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 876 the event of a WRAP event. 877 878 Work around the issue by always making sure we move the TRBPTR_EL1 by 879 256 bytes before enabling the buffer and filling the first 256 bytes of 880 the buffer with ETM ignore packets upon disabling. 881 882 If unsure, say Y. 883 884config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 885 bool 886 887config ARM64_ERRATUM_2054223 888 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 889 default y 890 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 891 help 892 Enable workaround for ARM Cortex-A710 erratum 2054223 893 894 Affected cores may fail to flush the trace data on a TSB instruction, when 895 the PE is in trace prohibited state. This will cause losing a few bytes 896 of the trace cached. 897 898 Workaround is to issue two TSB consecutively on affected cores. 899 900 If unsure, say Y. 901 902config ARM64_ERRATUM_2067961 903 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 904 default y 905 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 906 help 907 Enable workaround for ARM Neoverse-N2 erratum 2067961 908 909 Affected cores may fail to flush the trace data on a TSB instruction, when 910 the PE is in trace prohibited state. This will cause losing a few bytes 911 of the trace cached. 912 913 Workaround is to issue two TSB consecutively on affected cores. 914 915 If unsure, say Y. 916 917config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 918 bool 919 920config ARM64_ERRATUM_2253138 921 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 922 depends on CORESIGHT_TRBE 923 default y 924 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 925 help 926 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 927 928 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 929 for TRBE. Under some conditions, the TRBE might generate a write to the next 930 virtually addressed page following the last page of the TRBE address space 931 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 932 933 Work around this in the driver by always making sure that there is a 934 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 935 936 If unsure, say Y. 937 938config ARM64_ERRATUM_2224489 939 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 940 depends on CORESIGHT_TRBE 941 default y 942 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 943 help 944 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 945 946 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 947 for TRBE. Under some conditions, the TRBE might generate a write to the next 948 virtually addressed page following the last page of the TRBE address space 949 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 950 951 Work around this in the driver by always making sure that there is a 952 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 953 954 If unsure, say Y. 955 956config ARM64_ERRATUM_2441009 957 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 958 select ARM64_WORKAROUND_REPEAT_TLBI 959 help 960 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 961 962 Under very rare circumstances, affected Cortex-A510 CPUs 963 may not handle a race between a break-before-make sequence on one 964 CPU, and another CPU accessing the same page. This could allow a 965 store to a page that has been unmapped. 966 967 Work around this by adding the affected CPUs to the list that needs 968 TLB sequences to be done twice. 969 970 If unsure, say N. 971 972config ARM64_ERRATUM_2064142 973 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 974 depends on CORESIGHT_TRBE 975 default y 976 help 977 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 978 979 Affected Cortex-A510 core might fail to write into system registers after the 980 TRBE has been disabled. Under some conditions after the TRBE has been disabled 981 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 982 and TRBTRG_EL1 will be ignored and will not be effected. 983 984 Work around this in the driver by executing TSB CSYNC and DSB after collection 985 is stopped and before performing a system register write to one of the affected 986 registers. 987 988 If unsure, say Y. 989 990config ARM64_ERRATUM_2038923 991 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 992 depends on CORESIGHT_TRBE 993 default y 994 help 995 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 996 997 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 998 prohibited within the CPU. As a result, the trace buffer or trace buffer state 999 might be corrupted. This happens after TRBE buffer has been enabled by setting 1000 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 1001 execution changes from a context, in which trace is prohibited to one where it 1002 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1003 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1004 the trace buffer state might be corrupted. 1005 1006 Work around this in the driver by preventing an inconsistent view of whether the 1007 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1008 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1009 two ISB instructions if no ERET is to take place. 1010 1011 If unsure, say Y. 1012 1013config ARM64_ERRATUM_1902691 1014 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1015 depends on CORESIGHT_TRBE 1016 default y 1017 help 1018 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1019 1020 Affected Cortex-A510 core might cause trace data corruption, when being written 1021 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1022 trace data. 1023 1024 Work around this problem in the driver by just preventing TRBE initialization on 1025 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1026 on such implementations. This will cover the kernel for any firmware that doesn't 1027 do this already. 1028 1029 If unsure, say Y. 1030 1031config ARM64_ERRATUM_2457168 1032 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1033 depends on ARM64_AMU_EXTN 1034 default y 1035 help 1036 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1037 1038 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1039 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1040 incorrectly giving a significantly higher output value. 1041 1042 Work around this problem by returning 0 when reading the affected counter in 1043 key locations that results in disabling all users of this counter. This effect 1044 is the same to firmware disabling affected counters. 1045 1046 If unsure, say Y. 1047 1048config ARM64_ERRATUM_2645198 1049 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1050 default y 1051 help 1052 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1053 1054 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1055 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1056 next instruction abort caused by permission fault. 1057 1058 Only user-space does executable to non-executable permission transition via 1059 mprotect() system call. Workaround the problem by doing a break-before-make 1060 TLB invalidation, for all changes to executable user space mappings. 1061 1062 If unsure, say Y. 1063 1064config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1065 bool 1066 1067config ARM64_ERRATUM_2966298 1068 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1069 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1070 default y 1071 help 1072 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1073 1074 On an affected Cortex-A520 core, a speculatively executed unprivileged 1075 load might leak data from a privileged level via a cache side channel. 1076 1077 Work around this problem by executing a TLBI before returning to EL0. 1078 1079 If unsure, say Y. 1080 1081config ARM64_ERRATUM_3117295 1082 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1083 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1084 default y 1085 help 1086 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1087 1088 On an affected Cortex-A510 core, a speculatively executed unprivileged 1089 load might leak data from a privileged level via a cache side channel. 1090 1091 Work around this problem by executing a TLBI before returning to EL0. 1092 1093 If unsure, say Y. 1094 1095config ARM64_ERRATUM_3194386 1096 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1097 default y 1098 help 1099 This option adds the workaround for the following errata: 1100 1101 * ARM Cortex-A76 erratum 3324349 1102 * ARM Cortex-A77 erratum 3324348 1103 * ARM Cortex-A78 erratum 3324344 1104 * ARM Cortex-A78C erratum 3324346 1105 * ARM Cortex-A78C erratum 3324347 1106 * ARM Cortex-A710 erratam 3324338 1107 * ARM Cortex-A715 errartum 3456084 1108 * ARM Cortex-A720 erratum 3456091 1109 * ARM Cortex-A725 erratum 3456106 1110 * ARM Cortex-X1 erratum 3324344 1111 * ARM Cortex-X1C erratum 3324346 1112 * ARM Cortex-X2 erratum 3324338 1113 * ARM Cortex-X3 erratum 3324335 1114 * ARM Cortex-X4 erratum 3194386 1115 * ARM Cortex-X925 erratum 3324334 1116 * ARM Neoverse-N1 erratum 3324349 1117 * ARM Neoverse N2 erratum 3324339 1118 * ARM Neoverse-N3 erratum 3456111 1119 * ARM Neoverse-V1 erratum 3324341 1120 * ARM Neoverse V2 erratum 3324336 1121 * ARM Neoverse-V3 erratum 3312417 1122 1123 On affected cores "MSR SSBS, #0" instructions may not affect 1124 subsequent speculative instructions, which may permit unexepected 1125 speculative store bypassing. 1126 1127 Work around this problem by placing a Speculation Barrier (SB) or 1128 Instruction Synchronization Barrier (ISB) after kernel changes to 1129 SSBS. The presence of the SSBS special-purpose register is hidden 1130 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1131 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1132 1133 If unsure, say Y. 1134 1135config CAVIUM_ERRATUM_22375 1136 bool "Cavium erratum 22375, 24313" 1137 default y 1138 help 1139 Enable workaround for errata 22375 and 24313. 1140 1141 This implements two gicv3-its errata workarounds for ThunderX. Both 1142 with a small impact affecting only ITS table allocation. 1143 1144 erratum 22375: only alloc 8MB table size 1145 erratum 24313: ignore memory access type 1146 1147 The fixes are in ITS initialization and basically ignore memory access 1148 type and table size provided by the TYPER and BASER registers. 1149 1150 If unsure, say Y. 1151 1152config CAVIUM_ERRATUM_23144 1153 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1154 depends on NUMA 1155 default y 1156 help 1157 ITS SYNC command hang for cross node io and collections/cpu mapping. 1158 1159 If unsure, say Y. 1160 1161config CAVIUM_ERRATUM_23154 1162 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1163 default y 1164 help 1165 The ThunderX GICv3 implementation requires a modified version for 1166 reading the IAR status to ensure data synchronization 1167 (access to icc_iar1_el1 is not sync'ed before and after). 1168 1169 It also suffers from erratum 38545 (also present on Marvell's 1170 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1171 spuriously presented to the CPU interface. 1172 1173 If unsure, say Y. 1174 1175config CAVIUM_ERRATUM_27456 1176 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1177 default y 1178 help 1179 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1180 instructions may cause the icache to become corrupted if it 1181 contains data for a non-current ASID. The fix is to 1182 invalidate the icache when changing the mm context. 1183 1184 If unsure, say Y. 1185 1186config CAVIUM_ERRATUM_30115 1187 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1188 default y 1189 help 1190 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1191 1.2, and T83 Pass 1.0, KVM guest execution may disable 1192 interrupts in host. Trapping both GICv3 group-0 and group-1 1193 accesses sidesteps the issue. 1194 1195 If unsure, say Y. 1196 1197config CAVIUM_TX2_ERRATUM_219 1198 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1199 default y 1200 help 1201 On Cavium ThunderX2, a load, store or prefetch instruction between a 1202 TTBR update and the corresponding context synchronizing operation can 1203 cause a spurious Data Abort to be delivered to any hardware thread in 1204 the CPU core. 1205 1206 Work around the issue by avoiding the problematic code sequence and 1207 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1208 trap handler performs the corresponding register access, skips the 1209 instruction and ensures context synchronization by virtue of the 1210 exception return. 1211 1212 If unsure, say Y. 1213 1214config FUJITSU_ERRATUM_010001 1215 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1216 default y 1217 help 1218 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1219 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1220 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1221 This fault occurs under a specific hardware condition when a 1222 load/store instruction performs an address translation using: 1223 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1224 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1225 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1226 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1227 1228 The workaround is to ensure these bits are clear in TCR_ELx. 1229 The workaround only affects the Fujitsu-A64FX. 1230 1231 If unsure, say Y. 1232 1233config HISILICON_ERRATUM_161600802 1234 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1235 default y 1236 help 1237 The HiSilicon Hip07 SoC uses the wrong redistributor base 1238 when issued ITS commands such as VMOVP and VMAPP, and requires 1239 a 128kB offset to be applied to the target address in this commands. 1240 1241 If unsure, say Y. 1242 1243config HISILICON_ERRATUM_162100801 1244 bool "Hip09 162100801 erratum support" 1245 default y 1246 help 1247 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1248 during unmapping operation, which will cause some vSGIs lost. 1249 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1250 after VMOVP. 1251 1252 If unsure, say Y. 1253 1254config QCOM_FALKOR_ERRATUM_1003 1255 bool "Falkor E1003: Incorrect translation due to ASID change" 1256 default y 1257 help 1258 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1259 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1260 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1261 then only for entries in the walk cache, since the leaf translation 1262 is unchanged. Work around the erratum by invalidating the walk cache 1263 entries for the trampoline before entering the kernel proper. 1264 1265config QCOM_FALKOR_ERRATUM_1009 1266 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1267 default y 1268 select ARM64_WORKAROUND_REPEAT_TLBI 1269 help 1270 On Falkor v1, the CPU may prematurely complete a DSB following a 1271 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1272 one more time to fix the issue. 1273 1274 If unsure, say Y. 1275 1276config QCOM_QDF2400_ERRATUM_0065 1277 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1278 default y 1279 help 1280 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1281 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1282 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1283 1284 If unsure, say Y. 1285 1286config QCOM_FALKOR_ERRATUM_E1041 1287 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1288 default y 1289 help 1290 Falkor CPU may speculatively fetch instructions from an improper 1291 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1292 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1293 1294 If unsure, say Y. 1295 1296config NVIDIA_CARMEL_CNP_ERRATUM 1297 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1298 default y 1299 help 1300 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1301 invalidate shared TLB entries installed by a different core, as it would 1302 on standard ARM cores. 1303 1304 If unsure, say Y. 1305 1306config ROCKCHIP_ERRATUM_3588001 1307 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1308 default y 1309 help 1310 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1311 This means, that its sharability feature may not be used, even though it 1312 is supported by the IP itself. 1313 1314 If unsure, say Y. 1315 1316config SOCIONEXT_SYNQUACER_PREITS 1317 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1318 default y 1319 help 1320 Socionext Synquacer SoCs implement a separate h/w block to generate 1321 MSI doorbell writes with non-zero values for the device ID. 1322 1323 If unsure, say Y. 1324 1325endmenu # "ARM errata workarounds via the alternatives framework" 1326 1327choice 1328 prompt "Page size" 1329 default ARM64_4K_PAGES 1330 help 1331 Page size (translation granule) configuration. 1332 1333config ARM64_4K_PAGES 1334 bool "4KB" 1335 select HAVE_PAGE_SIZE_4KB 1336 help 1337 This feature enables 4KB pages support. 1338 1339config ARM64_16K_PAGES 1340 bool "16KB" 1341 select HAVE_PAGE_SIZE_16KB 1342 help 1343 The system will use 16KB pages support. AArch32 emulation 1344 requires applications compiled with 16K (or a multiple of 16K) 1345 aligned segments. 1346 1347config ARM64_64K_PAGES 1348 bool "64KB" 1349 select HAVE_PAGE_SIZE_64KB 1350 help 1351 This feature enables 64KB pages support (4KB by default) 1352 allowing only two levels of page tables and faster TLB 1353 look-up. AArch32 emulation requires applications compiled 1354 with 64K aligned segments. 1355 1356endchoice 1357 1358choice 1359 prompt "Virtual address space size" 1360 default ARM64_VA_BITS_52 1361 help 1362 Allows choosing one of multiple possible virtual address 1363 space sizes. The level of translation table is determined by 1364 a combination of page size and virtual address space size. 1365 1366config ARM64_VA_BITS_36 1367 bool "36-bit" if EXPERT 1368 depends on PAGE_SIZE_16KB 1369 1370config ARM64_VA_BITS_39 1371 bool "39-bit" 1372 depends on PAGE_SIZE_4KB 1373 1374config ARM64_VA_BITS_42 1375 bool "42-bit" 1376 depends on PAGE_SIZE_64KB 1377 1378config ARM64_VA_BITS_47 1379 bool "47-bit" 1380 depends on PAGE_SIZE_16KB 1381 1382config ARM64_VA_BITS_48 1383 bool "48-bit" 1384 1385config ARM64_VA_BITS_52 1386 bool "52-bit" 1387 help 1388 Enable 52-bit virtual addressing for userspace when explicitly 1389 requested via a hint to mmap(). The kernel will also use 52-bit 1390 virtual addresses for its own mappings (provided HW support for 1391 this feature is available, otherwise it reverts to 48-bit). 1392 1393 NOTE: Enabling 52-bit virtual addressing in conjunction with 1394 ARMv8.3 Pointer Authentication will result in the PAC being 1395 reduced from 7 bits to 3 bits, which may have a significant 1396 impact on its susceptibility to brute-force attacks. 1397 1398 If unsure, select 48-bit virtual addressing instead. 1399 1400endchoice 1401 1402config ARM64_FORCE_52BIT 1403 bool "Force 52-bit virtual addresses for userspace" 1404 depends on ARM64_VA_BITS_52 && EXPERT 1405 help 1406 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1407 to maintain compatibility with older software by providing 48-bit VAs 1408 unless a hint is supplied to mmap. 1409 1410 This configuration option disables the 48-bit compatibility logic, and 1411 forces all userspace addresses to be 52-bit on HW that supports it. One 1412 should only enable this configuration option for stress testing userspace 1413 memory management code. If unsure say N here. 1414 1415config ARM64_VA_BITS 1416 int 1417 default 36 if ARM64_VA_BITS_36 1418 default 39 if ARM64_VA_BITS_39 1419 default 42 if ARM64_VA_BITS_42 1420 default 47 if ARM64_VA_BITS_47 1421 default 48 if ARM64_VA_BITS_48 1422 default 52 if ARM64_VA_BITS_52 1423 1424choice 1425 prompt "Physical address space size" 1426 default ARM64_PA_BITS_48 1427 help 1428 Choose the maximum physical address range that the kernel will 1429 support. 1430 1431config ARM64_PA_BITS_48 1432 bool "48-bit" 1433 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1434 1435config ARM64_PA_BITS_52 1436 bool "52-bit" 1437 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1438 help 1439 Enable support for a 52-bit physical address space, introduced as 1440 part of the ARMv8.2-LPA extension. 1441 1442 With this enabled, the kernel will also continue to work on CPUs that 1443 do not support ARMv8.2-LPA, but with some added memory overhead (and 1444 minor performance overhead). 1445 1446endchoice 1447 1448config ARM64_PA_BITS 1449 int 1450 default 48 if ARM64_PA_BITS_48 1451 default 52 if ARM64_PA_BITS_52 1452 1453config ARM64_LPA2 1454 def_bool y 1455 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1456 1457choice 1458 prompt "Endianness" 1459 default CPU_LITTLE_ENDIAN 1460 help 1461 Select the endianness of data accesses performed by the CPU. Userspace 1462 applications will need to be compiled and linked for the endianness 1463 that is selected here. 1464 1465config CPU_BIG_ENDIAN 1466 bool "Build big-endian kernel" 1467 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1468 depends on AS_IS_GNU || AS_VERSION >= 150000 1469 help 1470 Say Y if you plan on running a kernel with a big-endian userspace. 1471 1472config CPU_LITTLE_ENDIAN 1473 bool "Build little-endian kernel" 1474 help 1475 Say Y if you plan on running a kernel with a little-endian userspace. 1476 This is usually the case for distributions targeting arm64. 1477 1478endchoice 1479 1480config SCHED_MC 1481 bool "Multi-core scheduler support" 1482 help 1483 Multi-core scheduler support improves the CPU scheduler's decision 1484 making when dealing with multi-core CPU chips at a cost of slightly 1485 increased overhead in some places. If unsure say N here. 1486 1487config SCHED_CLUSTER 1488 bool "Cluster scheduler support" 1489 help 1490 Cluster scheduler support improves the CPU scheduler's decision 1491 making when dealing with machines that have clusters of CPUs. 1492 Cluster usually means a couple of CPUs which are placed closely 1493 by sharing mid-level caches, last-level cache tags or internal 1494 busses. 1495 1496config SCHED_SMT 1497 bool "SMT scheduler support" 1498 help 1499 Improves the CPU scheduler's decision making when dealing with 1500 MultiThreading at a cost of slightly increased overhead in some 1501 places. If unsure say N here. 1502 1503config NR_CPUS 1504 int "Maximum number of CPUs (2-4096)" 1505 range 2 4096 1506 default "512" 1507 1508config HOTPLUG_CPU 1509 bool "Support for hot-pluggable CPUs" 1510 select GENERIC_IRQ_MIGRATION 1511 help 1512 Say Y here to experiment with turning CPUs off and on. CPUs 1513 can be controlled through /sys/devices/system/cpu. 1514 1515# Common NUMA Features 1516config NUMA 1517 bool "NUMA Memory Allocation and Scheduler Support" 1518 select GENERIC_ARCH_NUMA 1519 select OF_NUMA 1520 select HAVE_SETUP_PER_CPU_AREA 1521 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1522 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1523 select USE_PERCPU_NUMA_NODE_ID 1524 help 1525 Enable NUMA (Non-Uniform Memory Access) support. 1526 1527 The kernel will try to allocate memory used by a CPU on the 1528 local memory of the CPU and add some more 1529 NUMA awareness to the kernel. 1530 1531config NODES_SHIFT 1532 int "Maximum NUMA Nodes (as a power of 2)" 1533 range 1 10 1534 default "4" 1535 depends on NUMA 1536 help 1537 Specify the maximum number of NUMA Nodes available on the target 1538 system. Increases memory reserved to accommodate various tables. 1539 1540source "kernel/Kconfig.hz" 1541 1542config ARCH_SPARSEMEM_ENABLE 1543 def_bool y 1544 select SPARSEMEM_VMEMMAP_ENABLE 1545 select SPARSEMEM_VMEMMAP 1546 1547config HW_PERF_EVENTS 1548 def_bool y 1549 depends on ARM_PMU 1550 1551# Supported by clang >= 7.0 or GCC >= 12.0.0 1552config CC_HAVE_SHADOW_CALL_STACK 1553 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1554 1555config PARAVIRT 1556 bool "Enable paravirtualization code" 1557 help 1558 This changes the kernel so it can modify itself when it is run 1559 under a hypervisor, potentially improving performance significantly 1560 over full virtualization. 1561 1562config PARAVIRT_TIME_ACCOUNTING 1563 bool "Paravirtual steal time accounting" 1564 select PARAVIRT 1565 help 1566 Select this option to enable fine granularity task steal time 1567 accounting. Time spent executing other tasks in parallel with 1568 the current vCPU is discounted from the vCPU power. To account for 1569 that, there can be a small performance impact. 1570 1571 If in doubt, say N here. 1572 1573config ARCH_SUPPORTS_KEXEC 1574 def_bool PM_SLEEP_SMP 1575 1576config ARCH_SUPPORTS_KEXEC_FILE 1577 def_bool y 1578 1579config ARCH_SELECTS_KEXEC_FILE 1580 def_bool y 1581 depends on KEXEC_FILE 1582 select HAVE_IMA_KEXEC if IMA 1583 1584config ARCH_SUPPORTS_KEXEC_SIG 1585 def_bool y 1586 1587config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1588 def_bool y 1589 1590config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1591 def_bool y 1592 1593config ARCH_SUPPORTS_CRASH_DUMP 1594 def_bool y 1595 1596config ARCH_DEFAULT_CRASH_DUMP 1597 def_bool y 1598 1599config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1600 def_bool CRASH_RESERVE 1601 1602config TRANS_TABLE 1603 def_bool y 1604 depends on HIBERNATION || KEXEC_CORE 1605 1606config XEN_DOM0 1607 def_bool y 1608 depends on XEN 1609 1610config XEN 1611 bool "Xen guest support on ARM64" 1612 depends on ARM64 && OF 1613 select SWIOTLB_XEN 1614 select PARAVIRT 1615 help 1616 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1617 1618# include/linux/mmzone.h requires the following to be true: 1619# 1620# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1621# 1622# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1623# 1624# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1625# ----+-------------------+--------------+----------------------+-------------------------+ 1626# 4K | 27 | 12 | 15 | 10 | 1627# 16K | 27 | 14 | 13 | 11 | 1628# 64K | 29 | 16 | 13 | 13 | 1629config ARCH_FORCE_MAX_ORDER 1630 int 1631 default "13" if ARM64_64K_PAGES 1632 default "11" if ARM64_16K_PAGES 1633 default "10" 1634 help 1635 The kernel page allocator limits the size of maximal physically 1636 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1637 defines the maximal power of two of number of pages that can be 1638 allocated as a single contiguous block. This option allows 1639 overriding the default setting when ability to allocate very 1640 large blocks of physically contiguous memory is required. 1641 1642 The maximal size of allocation cannot exceed the size of the 1643 section, so the value of MAX_PAGE_ORDER should satisfy 1644 1645 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1646 1647 Don't change if unsure. 1648 1649config UNMAP_KERNEL_AT_EL0 1650 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1651 default y 1652 help 1653 Speculation attacks against some high-performance processors can 1654 be used to bypass MMU permission checks and leak kernel data to 1655 userspace. This can be defended against by unmapping the kernel 1656 when running in userspace, mapping it back in on exception entry 1657 via a trampoline page in the vector table. 1658 1659 If unsure, say Y. 1660 1661config MITIGATE_SPECTRE_BRANCH_HISTORY 1662 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1663 default y 1664 help 1665 Speculation attacks against some high-performance processors can 1666 make use of branch history to influence future speculation. 1667 When taking an exception from user-space, a sequence of branches 1668 or a firmware call overwrites the branch history. 1669 1670config RODATA_FULL_DEFAULT_ENABLED 1671 bool "Apply r/o permissions of VM areas also to their linear aliases" 1672 default y 1673 help 1674 Apply read-only attributes of VM areas to the linear alias of 1675 the backing pages as well. This prevents code or read-only data 1676 from being modified (inadvertently or intentionally) via another 1677 mapping of the same memory page. This additional enhancement can 1678 be turned off at runtime by passing rodata=[off|on] (and turned on 1679 with rodata=full if this option is set to 'n') 1680 1681 This requires the linear region to be mapped down to pages, 1682 which may adversely affect performance in some cases. 1683 1684config ARM64_SW_TTBR0_PAN 1685 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1686 depends on !KCSAN 1687 select ARM64_PAN 1688 help 1689 Enabling this option prevents the kernel from accessing 1690 user-space memory directly by pointing TTBR0_EL1 to a reserved 1691 zeroed area and reserved ASID. The user access routines 1692 restore the valid TTBR0_EL1 temporarily. 1693 1694config ARM64_TAGGED_ADDR_ABI 1695 bool "Enable the tagged user addresses syscall ABI" 1696 default y 1697 help 1698 When this option is enabled, user applications can opt in to a 1699 relaxed ABI via prctl() allowing tagged addresses to be passed 1700 to system calls as pointer arguments. For details, see 1701 Documentation/arch/arm64/tagged-address-abi.rst. 1702 1703menuconfig COMPAT 1704 bool "Kernel support for 32-bit EL0" 1705 depends on ARM64_4K_PAGES || EXPERT 1706 select HAVE_UID16 1707 select OLD_SIGSUSPEND3 1708 select COMPAT_OLD_SIGACTION 1709 help 1710 This option enables support for a 32-bit EL0 running under a 64-bit 1711 kernel at EL1. AArch32-specific components such as system calls, 1712 the user helper functions, VFP support and the ptrace interface are 1713 handled appropriately by the kernel. 1714 1715 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1716 that you will only be able to execute AArch32 binaries that were compiled 1717 with page size aligned segments. 1718 1719 If you want to execute 32-bit userspace applications, say Y. 1720 1721if COMPAT 1722 1723config KUSER_HELPERS 1724 bool "Enable kuser helpers page for 32-bit applications" 1725 default y 1726 help 1727 Warning: disabling this option may break 32-bit user programs. 1728 1729 Provide kuser helpers to compat tasks. The kernel provides 1730 helper code to userspace in read only form at a fixed location 1731 to allow userspace to be independent of the CPU type fitted to 1732 the system. This permits binaries to be run on ARMv4 through 1733 to ARMv8 without modification. 1734 1735 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1736 1737 However, the fixed address nature of these helpers can be used 1738 by ROP (return orientated programming) authors when creating 1739 exploits. 1740 1741 If all of the binaries and libraries which run on your platform 1742 are built specifically for your platform, and make no use of 1743 these helpers, then you can turn this option off to hinder 1744 such exploits. However, in that case, if a binary or library 1745 relying on those helpers is run, it will not function correctly. 1746 1747 Say N here only if you are absolutely certain that you do not 1748 need these helpers; otherwise, the safe option is to say Y. 1749 1750config COMPAT_VDSO 1751 bool "Enable vDSO for 32-bit applications" 1752 depends on !CPU_BIG_ENDIAN 1753 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1754 select GENERIC_COMPAT_VDSO 1755 default y 1756 help 1757 Place in the process address space of 32-bit applications an 1758 ELF shared object providing fast implementations of gettimeofday 1759 and clock_gettime. 1760 1761 You must have a 32-bit build of glibc 2.22 or later for programs 1762 to seamlessly take advantage of this. 1763 1764config THUMB2_COMPAT_VDSO 1765 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1766 depends on COMPAT_VDSO 1767 default y 1768 help 1769 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1770 otherwise with '-marm'. 1771 1772config COMPAT_ALIGNMENT_FIXUPS 1773 bool "Fix up misaligned multi-word loads and stores in user space" 1774 1775menuconfig ARMV8_DEPRECATED 1776 bool "Emulate deprecated/obsolete ARMv8 instructions" 1777 depends on SYSCTL 1778 help 1779 Legacy software support may require certain instructions 1780 that have been deprecated or obsoleted in the architecture. 1781 1782 Enable this config to enable selective emulation of these 1783 features. 1784 1785 If unsure, say Y 1786 1787if ARMV8_DEPRECATED 1788 1789config SWP_EMULATION 1790 bool "Emulate SWP/SWPB instructions" 1791 help 1792 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1793 they are always undefined. Say Y here to enable software 1794 emulation of these instructions for userspace using LDXR/STXR. 1795 This feature can be controlled at runtime with the abi.swp 1796 sysctl which is disabled by default. 1797 1798 In some older versions of glibc [<=2.8] SWP is used during futex 1799 trylock() operations with the assumption that the code will not 1800 be preempted. This invalid assumption may be more likely to fail 1801 with SWP emulation enabled, leading to deadlock of the user 1802 application. 1803 1804 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1805 on an external transaction monitoring block called a global 1806 monitor to maintain update atomicity. If your system does not 1807 implement a global monitor, this option can cause programs that 1808 perform SWP operations to uncached memory to deadlock. 1809 1810 If unsure, say Y 1811 1812config CP15_BARRIER_EMULATION 1813 bool "Emulate CP15 Barrier instructions" 1814 help 1815 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1816 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1817 strongly recommended to use the ISB, DSB, and DMB 1818 instructions instead. 1819 1820 Say Y here to enable software emulation of these 1821 instructions for AArch32 userspace code. When this option is 1822 enabled, CP15 barrier usage is traced which can help 1823 identify software that needs updating. This feature can be 1824 controlled at runtime with the abi.cp15_barrier sysctl. 1825 1826 If unsure, say Y 1827 1828config SETEND_EMULATION 1829 bool "Emulate SETEND instruction" 1830 help 1831 The SETEND instruction alters the data-endianness of the 1832 AArch32 EL0, and is deprecated in ARMv8. 1833 1834 Say Y here to enable software emulation of the instruction 1835 for AArch32 userspace code. This feature can be controlled 1836 at runtime with the abi.setend sysctl. 1837 1838 Note: All the cpus on the system must have mixed endian support at EL0 1839 for this feature to be enabled. If a new CPU - which doesn't support mixed 1840 endian - is hotplugged in after this feature has been enabled, there could 1841 be unexpected results in the applications. 1842 1843 If unsure, say Y 1844endif # ARMV8_DEPRECATED 1845 1846endif # COMPAT 1847 1848menu "ARMv8.1 architectural features" 1849 1850config ARM64_HW_AFDBM 1851 bool "Support for hardware updates of the Access and Dirty page flags" 1852 default y 1853 help 1854 The ARMv8.1 architecture extensions introduce support for 1855 hardware updates of the access and dirty information in page 1856 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1857 capable processors, accesses to pages with PTE_AF cleared will 1858 set this bit instead of raising an access flag fault. 1859 Similarly, writes to read-only pages with the DBM bit set will 1860 clear the read-only bit (AP[2]) instead of raising a 1861 permission fault. 1862 1863 Kernels built with this configuration option enabled continue 1864 to work on pre-ARMv8.1 hardware and the performance impact is 1865 minimal. If unsure, say Y. 1866 1867config ARM64_PAN 1868 bool "Enable support for Privileged Access Never (PAN)" 1869 default y 1870 help 1871 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1872 prevents the kernel or hypervisor from accessing user-space (EL0) 1873 memory directly. 1874 1875 Choosing this option will cause any unprotected (not using 1876 copy_to_user et al) memory access to fail with a permission fault. 1877 1878 The feature is detected at runtime, and will remain as a 'nop' 1879 instruction if the cpu does not implement the feature. 1880 1881config AS_HAS_LSE_ATOMICS 1882 def_bool $(as-instr,.arch_extension lse) 1883 1884config ARM64_LSE_ATOMICS 1885 bool 1886 default ARM64_USE_LSE_ATOMICS 1887 depends on AS_HAS_LSE_ATOMICS 1888 1889config ARM64_USE_LSE_ATOMICS 1890 bool "Atomic instructions" 1891 default y 1892 help 1893 As part of the Large System Extensions, ARMv8.1 introduces new 1894 atomic instructions that are designed specifically to scale in 1895 very large systems. 1896 1897 Say Y here to make use of these instructions for the in-kernel 1898 atomic routines. This incurs a small overhead on CPUs that do 1899 not support these instructions and requires the kernel to be 1900 built with binutils >= 2.25 in order for the new instructions 1901 to be used. 1902 1903endmenu # "ARMv8.1 architectural features" 1904 1905menu "ARMv8.2 architectural features" 1906 1907config AS_HAS_ARMV8_2 1908 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1909 1910config AS_HAS_SHA3 1911 def_bool $(as-instr,.arch armv8.2-a+sha3) 1912 1913config ARM64_PMEM 1914 bool "Enable support for persistent memory" 1915 select ARCH_HAS_PMEM_API 1916 select ARCH_HAS_UACCESS_FLUSHCACHE 1917 help 1918 Say Y to enable support for the persistent memory API based on the 1919 ARMv8.2 DCPoP feature. 1920 1921 The feature is detected at runtime, and the kernel will use DC CVAC 1922 operations if DC CVAP is not supported (following the behaviour of 1923 DC CVAP itself if the system does not define a point of persistence). 1924 1925config ARM64_RAS_EXTN 1926 bool "Enable support for RAS CPU Extensions" 1927 default y 1928 help 1929 CPUs that support the Reliability, Availability and Serviceability 1930 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1931 errors, classify them and report them to software. 1932 1933 On CPUs with these extensions system software can use additional 1934 barriers to determine if faults are pending and read the 1935 classification from a new set of registers. 1936 1937 Selecting this feature will allow the kernel to use these barriers 1938 and access the new registers if the system supports the extension. 1939 Platform RAS features may additionally depend on firmware support. 1940 1941config ARM64_CNP 1942 bool "Enable support for Common Not Private (CNP) translations" 1943 default y 1944 help 1945 Common Not Private (CNP) allows translation table entries to 1946 be shared between different PEs in the same inner shareable 1947 domain, so the hardware can use this fact to optimise the 1948 caching of such entries in the TLB. 1949 1950 Selecting this option allows the CNP feature to be detected 1951 at runtime, and does not affect PEs that do not implement 1952 this feature. 1953 1954endmenu # "ARMv8.2 architectural features" 1955 1956menu "ARMv8.3 architectural features" 1957 1958config ARM64_PTR_AUTH 1959 bool "Enable support for pointer authentication" 1960 default y 1961 help 1962 Pointer authentication (part of the ARMv8.3 Extensions) provides 1963 instructions for signing and authenticating pointers against secret 1964 keys, which can be used to mitigate Return Oriented Programming (ROP) 1965 and other attacks. 1966 1967 This option enables these instructions at EL0 (i.e. for userspace). 1968 Choosing this option will cause the kernel to initialise secret keys 1969 for each process at exec() time, with these keys being 1970 context-switched along with the process. 1971 1972 The feature is detected at runtime. If the feature is not present in 1973 hardware it will not be advertised to userspace/KVM guest nor will it 1974 be enabled. 1975 1976 If the feature is present on the boot CPU but not on a late CPU, then 1977 the late CPU will be parked. Also, if the boot CPU does not have 1978 address auth and the late CPU has then the late CPU will still boot 1979 but with the feature disabled. On such a system, this option should 1980 not be selected. 1981 1982config ARM64_PTR_AUTH_KERNEL 1983 bool "Use pointer authentication for kernel" 1984 default y 1985 depends on ARM64_PTR_AUTH 1986 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1987 # Modern compilers insert a .note.gnu.property section note for PAC 1988 # which is only understood by binutils starting with version 2.33.1. 1989 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1990 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1991 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1992 help 1993 If the compiler supports the -mbranch-protection or 1994 -msign-return-address flag (e.g. GCC 7 or later), then this option 1995 will cause the kernel itself to be compiled with return address 1996 protection. In this case, and if the target hardware is known to 1997 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1998 disabled with minimal loss of protection. 1999 2000 This feature works with FUNCTION_GRAPH_TRACER option only if 2001 DYNAMIC_FTRACE_WITH_ARGS is enabled. 2002 2003config CC_HAS_BRANCH_PROT_PAC_RET 2004 # GCC 9 or later, clang 8 or later 2005 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 2006 2007config CC_HAS_SIGN_RETURN_ADDRESS 2008 # GCC 7, 8 2009 def_bool $(cc-option,-msign-return-address=all) 2010 2011config AS_HAS_ARMV8_3 2012 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 2013 2014config AS_HAS_CFI_NEGATE_RA_STATE 2015 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2016 2017config AS_HAS_LDAPR 2018 def_bool $(as-instr,.arch_extension rcpc) 2019 2020endmenu # "ARMv8.3 architectural features" 2021 2022menu "ARMv8.4 architectural features" 2023 2024config ARM64_AMU_EXTN 2025 bool "Enable support for the Activity Monitors Unit CPU extension" 2026 default y 2027 help 2028 The activity monitors extension is an optional extension introduced 2029 by the ARMv8.4 CPU architecture. This enables support for version 1 2030 of the activity monitors architecture, AMUv1. 2031 2032 To enable the use of this extension on CPUs that implement it, say Y. 2033 2034 Note that for architectural reasons, firmware _must_ implement AMU 2035 support when running on CPUs that present the activity monitors 2036 extension. The required support is present in: 2037 * Version 1.5 and later of the ARM Trusted Firmware 2038 2039 For kernels that have this configuration enabled but boot with broken 2040 firmware, you may need to say N here until the firmware is fixed. 2041 Otherwise you may experience firmware panics or lockups when 2042 accessing the counter registers. Even if you are not observing these 2043 symptoms, the values returned by the register reads might not 2044 correctly reflect reality. Most commonly, the value read will be 0, 2045 indicating that the counter is not enabled. 2046 2047config AS_HAS_ARMV8_4 2048 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2049 2050config ARM64_TLB_RANGE 2051 bool "Enable support for tlbi range feature" 2052 default y 2053 depends on AS_HAS_ARMV8_4 2054 help 2055 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2056 range of input addresses. 2057 2058 The feature introduces new assembly instructions, and they were 2059 support when binutils >= 2.30. 2060 2061endmenu # "ARMv8.4 architectural features" 2062 2063menu "ARMv8.5 architectural features" 2064 2065config AS_HAS_ARMV8_5 2066 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2067 2068config ARM64_BTI 2069 bool "Branch Target Identification support" 2070 default y 2071 help 2072 Branch Target Identification (part of the ARMv8.5 Extensions) 2073 provides a mechanism to limit the set of locations to which computed 2074 branch instructions such as BR or BLR can jump. 2075 2076 To make use of BTI on CPUs that support it, say Y. 2077 2078 BTI is intended to provide complementary protection to other control 2079 flow integrity protection mechanisms, such as the Pointer 2080 authentication mechanism provided as part of the ARMv8.3 Extensions. 2081 For this reason, it does not make sense to enable this option without 2082 also enabling support for pointer authentication. Thus, when 2083 enabling this option you should also select ARM64_PTR_AUTH=y. 2084 2085 Userspace binaries must also be specifically compiled to make use of 2086 this mechanism. If you say N here or the hardware does not support 2087 BTI, such binaries can still run, but you get no additional 2088 enforcement of branch destinations. 2089 2090config ARM64_BTI_KERNEL 2091 bool "Use Branch Target Identification for kernel" 2092 default y 2093 depends on ARM64_BTI 2094 depends on ARM64_PTR_AUTH_KERNEL 2095 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2096 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2097 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2098 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2099 depends on !CC_IS_GCC 2100 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2101 help 2102 Build the kernel with Branch Target Identification annotations 2103 and enable enforcement of this for kernel code. When this option 2104 is enabled and the system supports BTI all kernel code including 2105 modular code must have BTI enabled. 2106 2107config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2108 # GCC 9 or later, clang 8 or later 2109 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2110 2111config ARM64_E0PD 2112 bool "Enable support for E0PD" 2113 default y 2114 help 2115 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2116 that EL0 accesses made via TTBR1 always fault in constant time, 2117 providing similar benefits to KASLR as those provided by KPTI, but 2118 with lower overhead and without disrupting legitimate access to 2119 kernel memory such as SPE. 2120 2121 This option enables E0PD for TTBR1 where available. 2122 2123config ARM64_AS_HAS_MTE 2124 # Initial support for MTE went in binutils 2.32.0, checked with 2125 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2126 # as a late addition to the final architecture spec (LDGM/STGM) 2127 # is only supported in the newer 2.32.x and 2.33 binutils 2128 # versions, hence the extra "stgm" instruction check below. 2129 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2130 2131config ARM64_MTE 2132 bool "Memory Tagging Extension support" 2133 default y 2134 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2135 depends on AS_HAS_ARMV8_5 2136 depends on AS_HAS_LSE_ATOMICS 2137 # Required for tag checking in the uaccess routines 2138 select ARM64_PAN 2139 select ARCH_HAS_SUBPAGE_FAULTS 2140 select ARCH_USES_HIGH_VMA_FLAGS 2141 select ARCH_USES_PG_ARCH_2 2142 select ARCH_USES_PG_ARCH_3 2143 help 2144 Memory Tagging (part of the ARMv8.5 Extensions) provides 2145 architectural support for run-time, always-on detection of 2146 various classes of memory error to aid with software debugging 2147 to eliminate vulnerabilities arising from memory-unsafe 2148 languages. 2149 2150 This option enables the support for the Memory Tagging 2151 Extension at EL0 (i.e. for userspace). 2152 2153 Selecting this option allows the feature to be detected at 2154 runtime. Any secondary CPU not implementing this feature will 2155 not be allowed a late bring-up. 2156 2157 Userspace binaries that want to use this feature must 2158 explicitly opt in. The mechanism for the userspace is 2159 described in: 2160 2161 Documentation/arch/arm64/memory-tagging-extension.rst. 2162 2163endmenu # "ARMv8.5 architectural features" 2164 2165menu "ARMv8.7 architectural features" 2166 2167config ARM64_EPAN 2168 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2169 default y 2170 depends on ARM64_PAN 2171 help 2172 Enhanced Privileged Access Never (EPAN) allows Privileged 2173 Access Never to be used with Execute-only mappings. 2174 2175 The feature is detected at runtime, and will remain disabled 2176 if the cpu does not implement the feature. 2177endmenu # "ARMv8.7 architectural features" 2178 2179config AS_HAS_MOPS 2180 def_bool $(as-instr,.arch_extension mops) 2181 2182menu "ARMv8.9 architectural features" 2183 2184config ARM64_POE 2185 prompt "Permission Overlay Extension" 2186 def_bool y 2187 select ARCH_USES_HIGH_VMA_FLAGS 2188 select ARCH_HAS_PKEYS 2189 help 2190 The Permission Overlay Extension is used to implement Memory 2191 Protection Keys. Memory Protection Keys provides a mechanism for 2192 enforcing page-based protections, but without requiring modification 2193 of the page tables when an application changes protection domains. 2194 2195 For details, see Documentation/core-api/protection-keys.rst 2196 2197 If unsure, say y. 2198 2199config ARCH_PKEY_BITS 2200 int 2201 default 3 2202 2203config ARM64_HAFT 2204 bool "Support for Hardware managed Access Flag for Table Descriptors" 2205 depends on ARM64_HW_AFDBM 2206 default y 2207 help 2208 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2209 Flag for Table descriptors. When enabled an architectural executed 2210 memory access will update the Access Flag in each Table descriptor 2211 which is accessed during the translation table walk and for which 2212 the Access Flag is 0. The Access Flag of the Table descriptor use 2213 the same bit of PTE_AF. 2214 2215 The feature will only be enabled if all the CPUs in the system 2216 support this feature. If unsure, say Y. 2217 2218endmenu # "ARMv8.9 architectural features" 2219 2220menu "v9.4 architectural features" 2221 2222config ARM64_GCS 2223 bool "Enable support for Guarded Control Stack (GCS)" 2224 default y 2225 select ARCH_HAS_USER_SHADOW_STACK 2226 select ARCH_USES_HIGH_VMA_FLAGS 2227 depends on !UPROBES 2228 help 2229 Guarded Control Stack (GCS) provides support for a separate 2230 stack with restricted access which contains only return 2231 addresses. This can be used to harden against some attacks 2232 by comparing return address used by the program with what is 2233 stored in the GCS, and may also be used to efficiently obtain 2234 the call stack for applications such as profiling. 2235 2236 The feature is detected at runtime, and will remain disabled 2237 if the system does not implement the feature. 2238 2239endmenu # "v9.4 architectural features" 2240 2241config ARM64_SVE 2242 bool "ARM Scalable Vector Extension support" 2243 default y 2244 help 2245 The Scalable Vector Extension (SVE) is an extension to the AArch64 2246 execution state which complements and extends the SIMD functionality 2247 of the base architecture to support much larger vectors and to enable 2248 additional vectorisation opportunities. 2249 2250 To enable use of this extension on CPUs that implement it, say Y. 2251 2252 On CPUs that support the SVE2 extensions, this option will enable 2253 those too. 2254 2255 Note that for architectural reasons, firmware _must_ implement SVE 2256 support when running on SVE capable hardware. The required support 2257 is present in: 2258 2259 * version 1.5 and later of the ARM Trusted Firmware 2260 * the AArch64 boot wrapper since commit 5e1261e08abf 2261 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2262 2263 For other firmware implementations, consult the firmware documentation 2264 or vendor. 2265 2266 If you need the kernel to boot on SVE-capable hardware with broken 2267 firmware, you may need to say N here until you get your firmware 2268 fixed. Otherwise, you may experience firmware panics or lockups when 2269 booting the kernel. If unsure and you are not observing these 2270 symptoms, you should assume that it is safe to say Y. 2271 2272config ARM64_SME 2273 bool "ARM Scalable Matrix Extension support" 2274 default y 2275 depends on ARM64_SVE 2276 depends on BROKEN 2277 help 2278 The Scalable Matrix Extension (SME) is an extension to the AArch64 2279 execution state which utilises a substantial subset of the SVE 2280 instruction set, together with the addition of new architectural 2281 register state capable of holding two dimensional matrix tiles to 2282 enable various matrix operations. 2283 2284config ARM64_PSEUDO_NMI 2285 bool "Support for NMI-like interrupts" 2286 select ARM_GIC_V3 2287 help 2288 Adds support for mimicking Non-Maskable Interrupts through the use of 2289 GIC interrupt priority. This support requires version 3 or later of 2290 ARM GIC. 2291 2292 This high priority configuration for interrupts needs to be 2293 explicitly enabled by setting the kernel parameter 2294 "irqchip.gicv3_pseudo_nmi" to 1. 2295 2296 If unsure, say N 2297 2298if ARM64_PSEUDO_NMI 2299config ARM64_DEBUG_PRIORITY_MASKING 2300 bool "Debug interrupt priority masking" 2301 help 2302 This adds runtime checks to functions enabling/disabling 2303 interrupts when using priority masking. The additional checks verify 2304 the validity of ICC_PMR_EL1 when calling concerned functions. 2305 2306 If unsure, say N 2307endif # ARM64_PSEUDO_NMI 2308 2309config RELOCATABLE 2310 bool "Build a relocatable kernel image" if EXPERT 2311 select ARCH_HAS_RELR 2312 default y 2313 help 2314 This builds the kernel as a Position Independent Executable (PIE), 2315 which retains all relocation metadata required to relocate the 2316 kernel binary at runtime to a different virtual address than the 2317 address it was linked at. 2318 Since AArch64 uses the RELA relocation format, this requires a 2319 relocation pass at runtime even if the kernel is loaded at the 2320 same address it was linked at. 2321 2322config RANDOMIZE_BASE 2323 bool "Randomize the address of the kernel image" 2324 select RELOCATABLE 2325 help 2326 Randomizes the virtual address at which the kernel image is 2327 loaded, as a security feature that deters exploit attempts 2328 relying on knowledge of the location of kernel internals. 2329 2330 It is the bootloader's job to provide entropy, by passing a 2331 random u64 value in /chosen/kaslr-seed at kernel entry. 2332 2333 When booting via the UEFI stub, it will invoke the firmware's 2334 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2335 to the kernel proper. In addition, it will randomise the physical 2336 location of the kernel Image as well. 2337 2338 If unsure, say N. 2339 2340config RANDOMIZE_MODULE_REGION_FULL 2341 bool "Randomize the module region over a 2 GB range" 2342 depends on RANDOMIZE_BASE 2343 default y 2344 help 2345 Randomizes the location of the module region inside a 2 GB window 2346 covering the core kernel. This way, it is less likely for modules 2347 to leak information about the location of core kernel data structures 2348 but it does imply that function calls between modules and the core 2349 kernel will need to be resolved via veneers in the module PLT. 2350 2351 When this option is not set, the module region will be randomized over 2352 a limited range that contains the [_stext, _etext] interval of the 2353 core kernel, so branch relocations are almost always in range unless 2354 the region is exhausted. In this particular case of region 2355 exhaustion, modules might be able to fall back to a larger 2GB area. 2356 2357config CC_HAVE_STACKPROTECTOR_SYSREG 2358 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2359 2360config STACKPROTECTOR_PER_TASK 2361 def_bool y 2362 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2363 2364config UNWIND_PATCH_PAC_INTO_SCS 2365 bool "Enable shadow call stack dynamically using code patching" 2366 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2367 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2368 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2369 depends on SHADOW_CALL_STACK 2370 select UNWIND_TABLES 2371 select DYNAMIC_SCS 2372 2373config ARM64_CONTPTE 2374 bool "Contiguous PTE mappings for user memory" if EXPERT 2375 depends on TRANSPARENT_HUGEPAGE 2376 default y 2377 help 2378 When enabled, user mappings are configured using the PTE contiguous 2379 bit, for any mappings that meet the size and alignment requirements. 2380 This reduces TLB pressure and improves performance. 2381 2382endmenu # "Kernel Features" 2383 2384menu "Boot options" 2385 2386config ARM64_ACPI_PARKING_PROTOCOL 2387 bool "Enable support for the ARM64 ACPI parking protocol" 2388 depends on ACPI 2389 help 2390 Enable support for the ARM64 ACPI parking protocol. If disabled 2391 the kernel will not allow booting through the ARM64 ACPI parking 2392 protocol even if the corresponding data is present in the ACPI 2393 MADT table. 2394 2395config CMDLINE 2396 string "Default kernel command string" 2397 default "" 2398 help 2399 Provide a set of default command-line options at build time by 2400 entering them here. As a minimum, you should specify the the 2401 root device (e.g. root=/dev/nfs). 2402 2403choice 2404 prompt "Kernel command line type" 2405 depends on CMDLINE != "" 2406 default CMDLINE_FROM_BOOTLOADER 2407 help 2408 Choose how the kernel will handle the provided default kernel 2409 command line string. 2410 2411config CMDLINE_FROM_BOOTLOADER 2412 bool "Use bootloader kernel arguments if available" 2413 help 2414 Uses the command-line options passed by the boot loader. If 2415 the boot loader doesn't provide any, the default kernel command 2416 string provided in CMDLINE will be used. 2417 2418config CMDLINE_FORCE 2419 bool "Always use the default kernel command string" 2420 help 2421 Always use the default kernel command string, even if the boot 2422 loader passes other arguments to the kernel. 2423 This is useful if you cannot or don't want to change the 2424 command-line options your boot loader passes to the kernel. 2425 2426endchoice 2427 2428config EFI_STUB 2429 bool 2430 2431config EFI 2432 bool "UEFI runtime support" 2433 depends on OF && !CPU_BIG_ENDIAN 2434 depends on KERNEL_MODE_NEON 2435 select ARCH_SUPPORTS_ACPI 2436 select LIBFDT 2437 select UCS2_STRING 2438 select EFI_PARAMS_FROM_FDT 2439 select EFI_RUNTIME_WRAPPERS 2440 select EFI_STUB 2441 select EFI_GENERIC_STUB 2442 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2443 default y 2444 help 2445 This option provides support for runtime services provided 2446 by UEFI firmware (such as non-volatile variables, realtime 2447 clock, and platform reset). A UEFI stub is also provided to 2448 allow the kernel to be booted as an EFI application. This 2449 is only useful on systems that have UEFI firmware. 2450 2451config COMPRESSED_INSTALL 2452 bool "Install compressed image by default" 2453 help 2454 This makes the regular "make install" install the compressed 2455 image we built, not the legacy uncompressed one. 2456 2457 You can check that a compressed image works for you by doing 2458 "make zinstall" first, and verifying that everything is fine 2459 in your environment before making "make install" do this for 2460 you. 2461 2462config DMI 2463 bool "Enable support for SMBIOS (DMI) tables" 2464 depends on EFI 2465 default y 2466 help 2467 This enables SMBIOS/DMI feature for systems. 2468 2469 This option is only useful on systems that have UEFI firmware. 2470 However, even with this option, the resultant kernel should 2471 continue to boot on existing non-UEFI platforms. 2472 2473endmenu # "Boot options" 2474 2475menu "Power management options" 2476 2477source "kernel/power/Kconfig" 2478 2479config ARCH_HIBERNATION_POSSIBLE 2480 def_bool y 2481 depends on CPU_PM 2482 2483config ARCH_HIBERNATION_HEADER 2484 def_bool y 2485 depends on HIBERNATION 2486 2487config ARCH_SUSPEND_POSSIBLE 2488 def_bool y 2489 2490endmenu # "Power management options" 2491 2492menu "CPU Power Management" 2493 2494source "drivers/cpuidle/Kconfig" 2495 2496source "drivers/cpufreq/Kconfig" 2497 2498endmenu # "CPU Power Management" 2499 2500source "drivers/acpi/Kconfig" 2501 2502source "arch/arm64/kvm/Kconfig" 2503 2504