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/linux/Documentation/devicetree/bindings/pci/
H A Dpci-msi.txt5 (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
6 Function number.
11 * Bits [15:8] are the Bus number.
12 * Bits [7:3] are the Device number.
13 * Bits [2:0] are the Function number.
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
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H A Dralink,rt3883-pci.txt1 * Mediatek/Ralink RT3883 PCI controller
7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
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/linux/Documentation/core-api/irq/
H A Dirq-domain.rst2 The irq_domain interrupt number mapping library
5 The current design of the Linux kernel uses a single large number
6 space where each separate IRQ source is assigned a different number.
7 This is simple when there is only one interrupt controller, but in
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
18 Here the interrupt number loose all kind of correspondence to
21 interrupt controller (i.e. the component actually fireing the
22 interrupt line to the CPU) nowadays this number is just a number.
24 For this reason we need a mechanism to separate controller-local
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 By using a serial interface, the SIO controller significantly extend
14 the number of available GPIOs with a minimum number of additional
17 controller.
21 pattern: "^gpio@[0-9a-f]+$"
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H A Dpinctrl-st.txt1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
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H A Dapple,pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple GPIO controller
10 - Mark Kettenis <kettenis@openbsd.org>
13 The Apple GPIO controller is a simple combined pin and GPIO
14 controller present on Apple ARM SoC platforms, including various
20 - enum:
21 - apple,t8103-pinctrl
22 - apple,t8112-pinctrl
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/linux/Documentation/devicetree/bindings/gpio/
H A Dnvidia,tegra186-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
20 The Tegra186 GPIO controller allows software to set the IO direction of,
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H A Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
42 The exact meaning of each specifier cell is controller specific, and must be
44 recommended to use the two-cell approach.
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H A Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB "UPG GIO" GPIO controller
10 The controller's registers are organized as sets of eight 32-bit
12 interrupt is shared for all of the banks handled by the controller.
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
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H A Dcdns,gpio.txt1 Cadence GPIO controller bindings
4 - compatible: should be "cdns,gpio-r1p02".
5 - reg: the register base address and size.
6 - #gpio-cells: should be 2.
7 * first cell is the GPIO number.
9 <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
11 - gpio-controller: marks the device as a GPIO controller.
12 - clocks: should contain one entry referencing the peripheral clock driving
13 the GPIO controller.
16 - ngpios: integer number of gpio lines supported by this controller, up to 32.
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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
44 * Bank type for non-alive type. Bit fields:
64 /* pin banks of exynos5433 pin-controller - ALIVE */
66 /* Must start with EINTG banks, ordered by EINT group number. */
78 /* pin banks of exynos5433 pin-controller - AUD */
80 /* Must start with EINTG banks, ordered by EINT group number. */
85 /* pin banks of exynos5433 pin-controller - CPIF */
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H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
90 * Samsung GPIO controller groups all the available pins into banks. The pins
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
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H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
35 /* Retention control for S5PV210 are located at the end of clock controller */
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
77 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
79 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
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/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-memory.json3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
8 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
14 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
19 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p…
30 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
41 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
51 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
61 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
66 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
72 …_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the to…
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/linux/Documentation/devicetree/bindings/firmware/
H A Dcznic,turris-omnia-mcu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
13 The MCU on Turris Omnia acts as a system controller providing additional
18 const: cznic,turris-omnia-mcu
27 interrupt-controller: true
29 '#interrupt-cells':
32 The first cell specifies the interrupt number (0 to 63), the second cell
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpic.txt2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
33 controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,omap2-intc.txt1 * OMAP Interrupt Controller
3 OMAP2/3 are using a TI interrupt controller that can support several
4 configurable number of interrupts.
8 - compatible : should be:
9 "ti,omap2-intc"
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
14 The cell contains the interrupt number in the range [0-128].
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
[all …]
H A Dti,cp-intc.txt1 * TI Common Platform Interrupt Controller
3 Common Platform Interrupt Controller (cp_intc) is used on
4 OMAP-L1x SoCs and can support several configurable number
9 - compatible : should be:
10 "ti,cp-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
15 The cell contains the interrupt number in the range [0-128].
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
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H A Darm,versatile-fpga-irq.txt1 * ARM Versatile FPGA interrupt controller
9 - compatible: "arm,versatile-fpga-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
12 as the FPGA IRQ controller has no configuration options for interrupt
13 sources. The cell is a u32 and defines the interrupt number.
14 - reg: The register bank for the FPGA interrupt controller.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
16 on the controller at boot for example.
17 - valid-mask: a u32 number representing a bit mask determining which of
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H A Dsamsung,exynos4210-combiner.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
21 usually connected to a parent interrupt controller.
[all …]
H A Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
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H A Dimg,pdc-intc.txt1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
4 representation of a PDC IRQ controller. This has a number of input interrupt
10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
17 as an interrupt controller. No property value shall be defined.
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
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H A Driscv,aplic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
14 platform level interrupt controller (APLIC) for handling wired interrupts
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-pxa-pci-ce4100.txt2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
11 number to its physical address and to use this to find the child nodes
12 of the specific I2C controller. This were his exact words:
22 non-zero if you had 2 or more devices mapped off
30 ------------------------------------------------
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/linux/drivers/usb/usbip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 be called usbip-core.
25 This enables the USB/IP virtual host controller driver,
29 module will be called vhci-hcd.
32 int "Number of ports per USB/IP virtual host controller"
37 To increase number of ports available for USB/IP virtual
38 host controller driver, this defines number of ports per
39 USB/IP virtual host controller.
42 int "Number of USB/IP virtual host controllers"
47 To increase number of ports available for USB/IP virtual
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