xref: /linux/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml (revision bf373e4c786bfe989e637195252698f45b157a68) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Nested Vector Interrupt Controller (NVIC)
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description:
13  The NVIC provides an interrupt controller that is tightly coupled to Cortex-M
14  based processor cores.  The NVIC implemented on different SoCs vary in the
15  number of interrupts and priority bits per interrupt.
16
17properties:
18  compatible:
19    enum:
20      - arm,v6m-nvic
21      - arm,v7m-nvic
22      - arm,v8m-nvic
23
24  reg:
25    maxItems: 1
26
27  '#address-cells':
28    const: 0
29
30  interrupt-controller: true
31
32  '#interrupt-cells':
33    const: 2
34    description: |
35      Number of cells to encode an interrupt source:
36      first = interrupt number, second = priority.
37
38  arm,num-irq-priority-bits:
39    description: Number of priority bits implemented by the SoC
40    minimum: 1
41    maximum: 8
42
43required:
44  - compatible
45  - reg
46  - interrupt-controller
47  - '#interrupt-cells'
48  - arm,num-irq-priority-bits
49
50additionalProperties: false
51
52examples:
53  - |
54    interrupt-controller@e000e100 {
55        compatible = "arm,v7m-nvic";
56        #interrupt-cells = <2>;
57        #address-cells = <0>;
58        interrupt-controller;
59        reg = <0xe000e100 0xc00>;
60        arm,num-irq-priority-bits = <4>;
61    };
62