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/linux/Documentation/scsi/
H A Dufs.rst1 .. SPDX-License-Identifier: GPL-2.0
21 5. UFS Reference Clock Frequency configuration
29 embedded and removable flash memory-based storage in mobile
32 on the MIPI M-PHY physical layer standard. UFS uses MIPI M-PHY as the
41 - Support for Gear1 is mandatory (rate A: 1248Mbps, rate B: 1457.6Mbps)
42 - Support for Gear2 is optional (rate A: 2496Mbps, rate B: 2915.2Mbps)
46 - Gear3 (rate A: 4992Mbps, rate B: 5830.4Mbps)
56 SAM-5 architectural model.
61 ---------------------
68 UFS supports a subset of SCSI commands defined by SPC-4 and SBC-3.
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/linux/include/linux/firmware/imx/svc/
H A Dpm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2017-2018 NXP
8 * control, clock control, reset control, and wake-up event control.
10 * PM_SVC (SVC) Power Management Service
12 * Module for the Power Management (PM) service.
56 #define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */
62 #define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */
63 #define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */
64 #define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */
65 #define IMX_SC_PM_CLK_PHY 3 /* Phy clock */
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/linux/arch/arm/boot/dts/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sdx55-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sdx55-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDX55 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SDX55 SoC Peripheral Authentication Service loads and boots firmware
19 - qcom,sdx55-mpss-pas
26 - description: XO clock
28 clock-names:
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H A Dqcom,qcs404-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCS404 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm QCS404 SoC Peripheral Authentication Service loads and boots
19 - qcom,qcs404-adsp-pas
20 - qcom,qcs404-cdsp-pas
21 - qcom,qcs404-wcss-pas
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H A Dqcom,sm6375-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm6375-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6375 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SM6375 SoC Peripheral Authentication Service loads and boots
19 - qcom,sm6375-adsp-pas
20 - qcom,sm6375-cdsp-pas
21 - qcom,sm6375-mpss-pas
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H A Dqcom,sc8280xp-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc8280xp-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC8280XP Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SC8280XP SoC Peripheral Authentication Service loads and boots
19 - qcom,sc8280xp-adsp-pas
20 - qcom,sc8280xp-nsp0-pas
21 - qcom,sc8280xp-nsp1-pas
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H A Dqcom,pas-common.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,pas-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Peripheral Authentication Service Common Properties
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Common properties of Qualcomm SoCs Peripheral Authentication Service.
20 clock-names:
30 - description: Watchdog interrupt
31 - description: Fatal interrupt
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H A Dqcom,sm6350-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm6350-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6350 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SM6350 SoC Peripheral Authentication Service loads and boots
19 - qcom,sm6350-adsp-pas
20 - qcom,sm6350-cdsp-pas
21 - qcom,sm6350-mpss-pas
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H A Dqcom,sa8775p-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sa8775p-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SA8775p Peripheral Authentication Service
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
13 Qualcomm SA8775p SoC Peripheral Authentication Service loads and boots firmware
19 - items:
20 - enum:
21 - qcom,qcs8300-adsp-pas
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H A Dqcom,sc7180-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7180/SC7280 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SC7180/SC7280 SoC Peripheral Authentication Service loads and boots
19 - qcom,sc7180-adsp-pas
20 - qcom,sc7180-mpss-pas
21 - qcom,sc7280-adsp-pas
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H A Dqcom,sm8150-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm8150-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8150/SM8250 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SM8150/SM8250 SoC Peripheral Authentication Service loads and boots
19 - items:
20 - enum:
21 - qcom,qcs615-adsp-pas
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/linux/tools/power/cpupower/
H A Dcpupower-service.conf1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # Copyright (C) 2024-2025, Francesco Poli <invernomuto@paranoici.org>
5 # Configuration file for cpupower.service systemd service unit
8 # your preferences) and then enable cpupower.service, if you want cpupower
11 # --- CPU clock frequency ---
27 # --- CPU policy ---
31 # the processor. See man CPUPOWER-SET(1) for additional details
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,apr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
20 - qcom,apr
21 - qcom,apr-v2
22 - qcom,gpr
24 power-domains:
27 qcom,apr-domain:
59 qcom,glink-channels:
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/linux/sound/arm/
H A Dpxa2xx-ac97-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
15 #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
19 #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
23 #define GCR_CLKBPB (1 << 31) /* Internal clock enable */
32 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
39 #define POSR_FSR (1 << 2) /* FIFO Service Request */
43 #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
44 #define PISR_FSR (1 << 2) /* FIFO Service Request */
48 #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
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/linux/include/linux/
H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
45 #define SSACD (0x3C) /* SSP Audio Clock Divider */
46 #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
55 #define SSCR0_ECS BIT(6) /* External clock select */
57 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
61 #define SSCR0_NCS BIT(21) /* Network clock select */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
67 #define SSCR0_ACS BIT(30) /* Audio clock select */
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/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
16 These requests include clock management, pin control, device control,
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
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/linux/arch/arm/mach-pxa/
H A Dirqs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-pxa/include/mach/irqs.h
17 #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
20 #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
23 #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
26 #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
29 #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
30 #define IRQ_USB PXA_IRQ(11) /* USB Service */
33 #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */
35 #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
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/linux/drivers/watchdog/
H A Ds32g_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2017-2019, 2021-2025 NXP.
18 #define DRIVER_NAME "s32g-swt"
21 #define S32G_SWT_CR_SM (BIT(9) | BIT(10)) /* -> Service Mode */
22 #define S32G_SWT_CR_STP BIT(2) /* -> Stop Mode Control */
23 #define S32G_SWT_CR_FRZ BIT(1) /* -> Debug Mode Control */
24 #define S32G_SWT_CR_WEN BIT(0) /* -> Watchdog Enable */
28 #define S32G_SWT_SR(__base) ((__base) + 0x10) /* Service Register offset */
29 #define S32G_WDT_SEQ1 0xA602 /* -> service sequence number 1 */
30 #define S32G_WDT_SEQ2 0xB480 /* -> service sequence number 2 */
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/linux/include/uapi/scsi/fc/
H A Dfc_els.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Maintained at www.Open-FCoE.org
21 * Fibre Channel Switch - Enhanced Link Services definitions.
22 * From T11 FC-LS Rev 1.2 June 7, 2005.
26 * ELS Command codes - byte 0 of the frame payload
34 ELS_ABTX = 0x06, /* Abort exchange - obsolet
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/linux/include/soc/fsl/
H A Ddpaa2-io.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2014-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2019 NXP
14 #include "dpaa2-fd.h"
15 #include "dpaa2-global.h"
22 * DOC: DPIO Service
24 * The DPIO service provides APIs for users to interact with the datapath
32 #define DPAA2_IO_ANY_CPU -1
35 * struct dpaa2_io_desc - The DPIO descriptor
36 * @receives_notifications: Use notificaton mode. Non-zero if the DPIO
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/linux/drivers/media/i2c/cx25840/
H A Dcx25840-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
122 * Rx and Tx Clock Divider register computations
124 * Note the largest clock divider value of 0xffff corresponds to:
135 d--; in count_to_clock_divider()
265 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
267 * The total pulse clock count is an 18 bit pulse width timer count as the most
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/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 booting process handling and offloading the power management, clock
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
28 This node is a clock, power domain, and reset provider. See the
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/linux/drivers/media/pci/cx23885/
H A Dcx23888-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
161 * Rx and Tx Clock Divider register computations
163 * Note the largest clock divider value of 0xffff corresponds to:
174 d--; in count_to_clock_divider()
278 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
280 * The total pulse clock count is an 18 bit pulse width timer count as the most
281 * significant part and (up to) 16 bit clock divider count as a modulus.
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/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,q6prm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 - $ref: /schemas/soc/qcom/qcom,apr-services.yaml#
19 - qcom,q6prm
21 clock-controller:
22 $ref: /schemas/sound/qcom,q6dsp-lpass-clocks.yaml#
24 description: Qualcomm DSP LPASS clock controller
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