1*8ff06452SArnd Bergmann /* SPDX-License-Identifier: GPL-2.0 */ 2*8ff06452SArnd Bergmann #ifndef __ASM_ARCH_REGS_AC97_H 3*8ff06452SArnd Bergmann #define __ASM_ARCH_REGS_AC97_H 4*8ff06452SArnd Bergmann 5*8ff06452SArnd Bergmann /* 6*8ff06452SArnd Bergmann * AC97 Controller registers 7*8ff06452SArnd Bergmann */ 8*8ff06452SArnd Bergmann 9*8ff06452SArnd Bergmann #define POCR (0x0000) /* PCM Out Control Register */ 10*8ff06452SArnd Bergmann #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ 11*8ff06452SArnd Bergmann #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 12*8ff06452SArnd Bergmann 13*8ff06452SArnd Bergmann #define PICR (0x0004) /* PCM In Control Register */ 14*8ff06452SArnd Bergmann #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ 15*8ff06452SArnd Bergmann #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 16*8ff06452SArnd Bergmann 17*8ff06452SArnd Bergmann #define MCCR (0x0008) /* Mic In Control Register */ 18*8ff06452SArnd Bergmann #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ 19*8ff06452SArnd Bergmann #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 20*8ff06452SArnd Bergmann 21*8ff06452SArnd Bergmann #define GCR (0x000C) /* Global Control Register */ 22*8ff06452SArnd Bergmann #ifdef CONFIG_PXA3xx 23*8ff06452SArnd Bergmann #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ 24*8ff06452SArnd Bergmann #endif 25*8ff06452SArnd Bergmann #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ 26*8ff06452SArnd Bergmann #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ 27*8ff06452SArnd Bergmann #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ 28*8ff06452SArnd Bergmann #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ 29*8ff06452SArnd Bergmann #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ 30*8ff06452SArnd Bergmann #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ 31*8ff06452SArnd Bergmann #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ 32*8ff06452SArnd Bergmann #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ 33*8ff06452SArnd Bergmann #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ 34*8ff06452SArnd Bergmann #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ 35*8ff06452SArnd Bergmann #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ 36*8ff06452SArnd Bergmann 37*8ff06452SArnd Bergmann #define POSR (0x0010) /* PCM Out Status Register */ 38*8ff06452SArnd Bergmann #define POSR_FIFOE (1 << 4) /* FIFO error */ 39*8ff06452SArnd Bergmann #define POSR_FSR (1 << 2) /* FIFO Service Request */ 40*8ff06452SArnd Bergmann 41*8ff06452SArnd Bergmann #define PISR (0x0014) /* PCM In Status Register */ 42*8ff06452SArnd Bergmann #define PISR_FIFOE (1 << 4) /* FIFO error */ 43*8ff06452SArnd Bergmann #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ 44*8ff06452SArnd Bergmann #define PISR_FSR (1 << 2) /* FIFO Service Request */ 45*8ff06452SArnd Bergmann 46*8ff06452SArnd Bergmann #define MCSR (0x0018) /* Mic In Status Register */ 47*8ff06452SArnd Bergmann #define MCSR_FIFOE (1 << 4) /* FIFO error */ 48*8ff06452SArnd Bergmann #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ 49*8ff06452SArnd Bergmann #define MCSR_FSR (1 << 2) /* FIFO Service Request */ 50*8ff06452SArnd Bergmann 51*8ff06452SArnd Bergmann #define GSR (0x001C) /* Global Status Register */ 52*8ff06452SArnd Bergmann #define GSR_CDONE (1 << 19) /* Command Done */ 53*8ff06452SArnd Bergmann #define GSR_SDONE (1 << 18) /* Status Done */ 54*8ff06452SArnd Bergmann #define GSR_RDCS (1 << 15) /* Read Completion Status */ 55*8ff06452SArnd Bergmann #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ 56*8ff06452SArnd Bergmann #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ 57*8ff06452SArnd Bergmann #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ 58*8ff06452SArnd Bergmann #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ 59*8ff06452SArnd Bergmann #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ 60*8ff06452SArnd Bergmann #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ 61*8ff06452SArnd Bergmann #define GSR_PCR (1 << 8) /* Primary Codec Ready */ 62*8ff06452SArnd Bergmann #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ 63*8ff06452SArnd Bergmann #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ 64*8ff06452SArnd Bergmann #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ 65*8ff06452SArnd Bergmann #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ 66*8ff06452SArnd Bergmann #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ 67*8ff06452SArnd Bergmann #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ 68*8ff06452SArnd Bergmann #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ 69*8ff06452SArnd Bergmann 70*8ff06452SArnd Bergmann #define CAR (0x0020) /* CODEC Access Register */ 71*8ff06452SArnd Bergmann #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ 72*8ff06452SArnd Bergmann 73*8ff06452SArnd Bergmann #define PCDR (0x0040) /* PCM FIFO Data Register */ 74*8ff06452SArnd Bergmann #define MCDR (0x0060) /* Mic-in FIFO Data Register */ 75*8ff06452SArnd Bergmann 76*8ff06452SArnd Bergmann #define MOCR (0x0100) /* Modem Out Control Register */ 77*8ff06452SArnd Bergmann #define MOCR_FEIE (1 << 3) /* FIFO Error */ 78*8ff06452SArnd Bergmann #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 79*8ff06452SArnd Bergmann 80*8ff06452SArnd Bergmann #define MICR (0x0108) /* Modem In Control Register */ 81*8ff06452SArnd Bergmann #define MICR_FEIE (1 << 3) /* FIFO Error */ 82*8ff06452SArnd Bergmann #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 83*8ff06452SArnd Bergmann 84*8ff06452SArnd Bergmann #define MOSR (0x0110) /* Modem Out Status Register */ 85*8ff06452SArnd Bergmann #define MOSR_FIFOE (1 << 4) /* FIFO error */ 86*8ff06452SArnd Bergmann #define MOSR_FSR (1 << 2) /* FIFO Service Request */ 87*8ff06452SArnd Bergmann 88*8ff06452SArnd Bergmann #define MISR (0x0118) /* Modem In Status Register */ 89*8ff06452SArnd Bergmann #define MISR_FIFOE (1 << 4) /* FIFO error */ 90*8ff06452SArnd Bergmann #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ 91*8ff06452SArnd Bergmann #define MISR_FSR (1 << 2) /* FIFO Service Request */ 92*8ff06452SArnd Bergmann 93*8ff06452SArnd Bergmann #define MODR (0x0140) /* Modem FIFO Data Register */ 94*8ff06452SArnd Bergmann 95*8ff06452SArnd Bergmann #define PAC_REG_BASE (0x0200) /* Primary Audio Codec */ 96*8ff06452SArnd Bergmann #define SAC_REG_BASE (0x0300) /* Secondary Audio Codec */ 97*8ff06452SArnd Bergmann #define PMC_REG_BASE (0x0400) /* Primary Modem Codec */ 98*8ff06452SArnd Bergmann #define SMC_REG_BASE (0x0500) /* Secondary Modem Codec */ 99*8ff06452SArnd Bergmann 100*8ff06452SArnd Bergmann #endif /* __ASM_ARCH_REGS_AC97_H */ 101