1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * Copyright 2017-2019, 2021-2025 NXP.
18 #define DRIVER_NAME "s32g-swt"
21 #define S32G_SWT_CR_SM		(BIT(9) | BIT(10))	/* -> Service Mode		*/
22 #define S32G_SWT_CR_STP		BIT(2)			/* -> Stop Mode Control		*/
23 #define S32G_SWT_CR_FRZ		BIT(1)			/* -> Debug Mode Control	*/
24 #define S32G_SWT_CR_WEN		BIT(0)			/* -> Watchdog Enable		*/
28 #define S32G_SWT_SR(__base)	((__base) + 0x10)	/* Service Register offset	*/
29 #define S32G_WDT_SEQ1		0xA602			/* -> service sequence number 1	*/
30 #define S32G_WDT_SEQ2		0xB480			/* -> service sequence number 2	*/
70 	return wdev->rate * timeout;  in wdog_sec_to_count()
77 	writel(S32G_WDT_SEQ1, S32G_SWT_SR(wdev->base));  in s32g_wdt_ping()
78 	writel(S32G_WDT_SEQ2, S32G_SWT_SR(wdev->base));  in s32g_wdt_ping()
88 	val = readl(S32G_SWT_CR(wdev->base));  in s32g_wdt_start()
92 	writel(val, S32G_SWT_CR(wdev->base));  in s32g_wdt_start()
102 	val = readl(S32G_SWT_CR(wdev->base));  in s32g_wdt_stop()
106 	writel(val, S32G_SWT_CR(wdev->base));  in s32g_wdt_stop()
115 	writel(wdog_sec_to_count(wdev, timeout), S32G_SWT_TO(wdev->base));  in s32g_wdt_set_timeout()
117 	wdog->timeout = timeout;  in s32g_wdt_set_timeout()
149 	counter = readl(S32G_SWT_CO(wdev->base));  in s32g_wdt_get_timeleft()
154 	return counter / wdev->rate;  in s32g_wdt_get_timeleft()
170 	/* Set the watchdog's Time-Out value */  in s32g_wdt_init()
171 	val = wdog_sec_to_count(wdev, wdev->wdog.timeout);  in s32g_wdt_init()
173 	writel(val, S32G_SWT_TO(wdev->base));  in s32g_wdt_init()
179 	val = readl(S32G_SWT_CR(wdev->base));  in s32g_wdt_init()
195 	 * Use Fixed Service Sequence to ping the watchdog which is  in s32g_wdt_init()
196 	 * 0x00 configuration value for the service mode. It should be  in s32g_wdt_init()
202 	writel(val, S32G_SWT_CR(wdev->base));  in s32g_wdt_init()
209 		s32g_wdt_start(&wdev->wdog);  in s32g_wdt_init()
210 		set_bit(WDOG_HW_RUNNING, &wdev->wdog.status);  in s32g_wdt_init()
216 	struct device *dev = &pdev->dev;  in s32g_wdt_probe()
225 		return -ENOMEM;  in s32g_wdt_probe()
228 	wdev->base = devm_ioremap_resource(dev, res);  in s32g_wdt_probe()
229 	if (IS_ERR(wdev->base))  in s32g_wdt_probe()
230 		return dev_err_probe(&pdev->dev, PTR_ERR(wdev->base), "Can not get resource\n");  in s32g_wdt_probe()
234 		return dev_err_probe(dev, PTR_ERR(clk), "Can't get Watchdog clock\n");  in s32g_wdt_probe()
236 	wdev->rate = clk_get_rate(clk);  in s32g_wdt_probe()
237 	if (!wdev->rate) {  in s32g_wdt_probe()
238 		dev_err(dev, "Input clock rate is not valid\n");  in s32g_wdt_probe()
239 		return -EINVAL;  in s32g_wdt_probe()
242 	wdog = &wdev->wdog;  in s32g_wdt_probe()
243 	wdog->info = &s32g_wdt_info;  in s32g_wdt_probe()
244 	wdog->ops = &s32g_wdt_ops;  in s32g_wdt_probe()
252 	wdog->min_timeout = 0;  in s32g_wdt_probe()
262 	wdog->max_timeout = UINT_MAX / wdev->rate;  in s32g_wdt_probe()
265 	 * The module param and the DT 'timeout-sec' property will  in s32g_wdt_probe()
292 		 wdog->timeout, nowayout, early_enable);  in s32g_wdt_probe()
298 	{ .compatible = "nxp,s32g2-swt" },