Lines Matching +full:clock +full:- +full:service
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
45 #define SSACD (0x3C) /* SSP Audio Clock Divider */
46 #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
55 #define SSCR0_ECS BIT(6) /* External clock select */
57 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
61 #define SSCR0_NCS BIT(21) /* Network clock select */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
67 #define SSCR0_ACS BIT(30) /* Audio clock select */
72 #define SSCR1_LBM BIT(2) /* Loop-Back Mode */
81 #define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */
82 #define SSSR_RFS BIT(6) /* Receive FIFO Service Request */
92 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
94 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
103 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
105 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
108 #define DDS_RATE 0x28 /* SSP DDS Clock Rate Register */
112 #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
123 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */
125 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */
131 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
137 #define SSCR1_TINTE BIT(19) /* Receiver Time-out Interrupt enable */
138 #define SSCR1_RSRE BIT(20) /* Receive Service Request Enable */
139 #define SSCR1_TSRE BIT(21) /* Transmit Service Request Enable */
143 #define SSCR1_SCLKDIR BIT(25) /* Serial Bit Rate Clock Direction */
144 #define SSCR1_ECRB BIT(26) /* Enable Clock request B */
145 #define SSCR1_ECRA BIT(27) /* Enable Clock Request A */
146 #define SSCR1_SCFR BIT(28) /* Slave Clock free Running */
152 #define SSSR_TINT BIT(19) /* Receiver Time-out Interrupt */
155 #define SSSR_CSS BIT(22) /* Clock Synchronisation Status */
158 #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
173 #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
183 #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
197 #define SFIFOTT_TxThresh(x) (((x) - 1) << 0) /* TX FIFO trigger threshold / level */
199 #define SFIFOTT_RxThresh(x) (((x) - 1) << 16) /* RX FIFO trigger threshold / level */
203 #define SSITF_TxHiThresh(x) (((x) - 1) << 0)
204 #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
207 #define SSIRF_RxThresh(x) ((x) - 1)
253 * pxa_ssp_write_reg - Write to a SSP register
261 __raw_writel(val, dev->mmio_base + reg); in pxa_ssp_write_reg()
265 * pxa_ssp_read_reg - Read from a SSP register
272 return __raw_readl(dev->mmio_base + reg); in pxa_ssp_read_reg()