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/freebsd/sys/arm/arm/
H A Dgic_fdt.c1 /*-
60 struct arm_gic_softc base; member
72 {"arm,gic", true}, /* Non-standard, used in FreeBSD dts. */
73 {"arm,gic-400", true},
74 {"arm,cortex-a15-gic", true},
75 {"arm,cortex-a9-gic", true},
76 {"arm,cortex-a7-gic", true},
77 {"arm,arm11mp-gic", true},
78 {"brcm,brahma-b15-gic", true},
79 {"qcom,msm-qgic2", true},
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dsamsung-pinctrl.txt6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
[all …]
H A Dbrcm,nsp-gpio.txt4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
9 GPIO base, IO control registers
11 - #gpio-cells:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
24 Interrupt ID
26 - interrupt-controller:
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H A Dbrcm,iproc-gpio.txt5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
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/freebsd/sys/dev/bhnd/bhndb/
H A Dbhndb_if.m1 #-
2 # Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
57 bhndb_null_get_chipid(device_t dev, device_t child)
63 bhndb_null_populate_board_info(device_t dev, device_t child,
70 bhndb_null_is_core_disabled(device_t dev, device_t child,
77 bhndb_null_get_hostb_core(device_t dev, device_t child,
84 bhndb_null_suspend_resource(device_t dev, device_t child, int type,
91 bhndb_null_resume_resource(device_t dev, device_t child, int type,
98 bhndb_null_route_interrupts(device_t dev, device_t child)
119 * Return the chip identification information for @p child.
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/freebsd/sys/dev/bhnd/siba/
H A Dsiba_subr.c1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
48 static int siba_register_interrupts(device_t dev, device_t child,
51 uint8_t addridx, uint32_t base, uint32_t size,
55 * Map a siba(4) OCP vendor code to its corresponding JEDEC JEP-106 vendor
89 for (u_int i = 0; i < nitems(dinfo->cfg); i++) { in siba_alloc_dinfo()
90 dinfo->cfg[i] = ((struct siba_cfg_block){ in siba_alloc_dinfo()
93 .cb_rid = -1, in siba_alloc_dinfo()
95 dinfo->cfg_res[i] = NULL; in siba_alloc_dinfo()
96 dinfo->cfg_rid[i] = -1; in siba_alloc_dinfo()
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H A Dsibavar.h1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
66 u_int siba_get_intr_count(device_t dev, device_t child);
67 int siba_get_intr_ivec(device_t dev, device_t child,
75 int siba_init_dinfo(device_t dev, device_t child,
78 void siba_free_dinfo(device_t dev, device_t child,
128 #define SIBA_CFG_RID_BASE 100 /**< base resource ID for SIBA_CFG* register allocations */
131 (_dinfo->core_id.core_info.core_idx * SIBA_MAX_CFG))
147 uint32_t am_base; /**< base address. */
155 uint32_t sa_base; /**< base address */
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcci.txt5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
35 of cells, containing base and size.
36 Definition: A standard property. Specifies base physical
40 - ranges:
43 as a tuple of cells, containing child address,
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dst,stih4xx.txt3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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/freebsd/sys/dev/xilinx/
H A Dxlnx_pcib.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
98 { -1, 0 }
113 reg = bus_read_4(sc->res, XLNX_PCIE_RPERRFRR); in xlnx_pcib_clear_err_interrupts()
116 device_printf(sc->dev, "Requested ID: %x\n", in xlnx_pcib_clear_err_interrupts()
118 bus_write_4(sc->res, XLNX_PCIE_RPERRFRR, ~0U); in xlnx_pcib_clear_err_interrupts()
131 fdt_sc = &xlnx_sc->fdt_sc; in xlnx_pcib_intr()
132 sc = &fdt_sc->base; in xlnx_pcib_intr()
134 val = bus_read_4(sc->res, XLNX_PCIE_IDR); in xlnx_pcib_intr()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
[all …]
H A Dralink,rt3883-pci.txt7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
26 2) Child nodes
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
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/freebsd/sys/contrib/device-tree/Bindings/soc/dove/
H A Dpmu.txt4 - compatible: value should be "marvell,dove-pmu".
5 May also include "simple-bus" if there are child devices, in which
7 - reg: two base addresses and sizes of the PM controller and PMU.
8 - interrupts: single interrupt number for the PMU interrupt
9 - interrupt-controller: must be specified as the PMU itself is an
10 interrupt controller.
11 - #interrupt-cells: must be 1.
12 - #reset-cells: must be 1.
13 - domains: sub-node containing domain descriptions
16 - ranges: defines the address mapping for child devices, as per the
[all …]
/freebsd/sys/dev/scc/
H A Dscc_core.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2004-2006 Marcel Moolenaar
62 cl = sc->sc_class; in scc_bfe_intr()
63 while (!sc->sc_leaving && (ipend = SCC_IPEND(sc)) != 0) { in scc_bfe_intr()
70 for (c = 0; c < cl->cl_channels; c++) { in scc_bfe_intr()
71 ch = &sc->sc_cha in scc_bfe_intr()
106 rman_res_t base, size, start, sz; scc_bfe_attach() local
409 scc_bus_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags) scc_bus_alloc_resource() argument
433 scc_bus_get_resource(device_t dev,device_t child,int type,int rid,rman_res_t * startp,rman_res_t * countp) scc_bus_get_resource() argument
457 scc_bus_read_ivar(device_t dev,device_t child,int index,uintptr_t * result) scc_bus_read_ivar() argument
498 scc_bus_release_resource(device_t dev,device_t child,struct resource * res) scc_bus_release_resource() argument
515 scc_bus_setup_intr(device_t dev,device_t child,struct resource * r,int flags,driver_filter_t * filt,void (* ihand)(void *),void * arg,void ** cookiep) scc_bus_setup_intr() argument
564 scc_bus_teardown_intr(device_t dev,device_t child,struct resource * r,void * cookie) scc_bus_teardown_intr() argument
[all...]
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dkeystone-navigator-qmss.txt5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
32 -- managed-queues : the actual queues managed by each queue manager
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
/freebsd/sys/arm64/rockchip/
H A Drk_pcie.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
78 #define ATU_OB_REGION_0_SIZE (( ATU_OB_REGIONS - 1) * ATU_OB_REGION_SIZE)
179 #define APB_WR4(_sc, _r, _v) bus_write_4((_sc)->apb_mem_res, (_r), (_v))
180 #define APB_RD4(_sc, _r) bus_read_4((_sc)->apb_mem_res, (_r))
240 {"rockchip,rk3399-pcie", 1},
249 bus_addr_t base; in rk_pcie_local_cfg_read() local
252 base = PCIE_RC_CONFIG_PRIV_BASE; in rk_pcie_local_cfg_read()
254 base = PCIE_RC_CONFIG_STD_BASE; in rk_pcie_local_cfg_read()
258 val = bus_read_4(sc->apb_mem_res, base + reg); in rk_pcie_local_cfg_read()
[all …]
/freebsd/sys/dev/bhnd/bcma/
H A Dbcmavar.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
53 /** Base resource ID for per-core agent register allocations */
62 ((_dinfo)->corecfg->core_info.core_idx)
68 /** BCMA per-port region map identifier. */
82 u_int bcma_get_intr_count(device_t dev, device_t child);
83 int bcma_get_intr_ivec(device_t dev, device_t child,
92 int bcma_init_dinfo(device_t bus, device_t child,
95 void bcma_free_dinfo(device_t bus, device_t child,
[all …]
/freebsd/sys/dev/pci/
H A Dpci_pci.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
71 static int pcib_reset_child(device_t dev, device_t child, int flags);
147 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
150 * Get the corresponding window if this resource from a child device was
151 * sub-allocated from one of our window resource managers.
158 if (rman_is_region_manager(r, &sc->io.rman)) in pcib_get_resource_window()
159 return (&sc->io); in pcib_get_resource_window()
164 rman_is_region_manager(r, &sc->pmem.rman)) in pcib_get_resource_window()
165 return (&sc->pmem); in pcib_get_resource_window()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dmarvell.txt2 ----------
[all...]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Docteon-usb.txt7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
31 2) Child node
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Domap-mailbox.txt5 using a queued mailbox interrupt mechanism. The IP block is external to the
8 interrupt configuration registers.
11 interrupt lines. An output interrupt line is routed to an interrupt controller
13 specific processor's interrupt controller. The interrupt line connections are
15 (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
16 programmable through a set of interrupt configuration registers, and have a rx
17 and tx interrupt source per h/w fifo. Communication between different processors
18 is achieved through the appropriate programming of the rx and tx interrupt
19 sources on the appropriate interrupt lines.
21 The number of h/w fifo queues and interrupt lines dictate the usable registers.
[all …]
/freebsd/lib/libsys/
H A Dsigaction.238 .Bd -literal
55 Signal delivery resembles the occurrence of a hardware interrupt:
73 This may be changed, on a per-handler basis,
108 (e.g., during a system call, page fault or trap, or clock interrupt).
112 appearing to interrupt the handlers for the previous signals
144 is non-NULL, it specifies an action
150 is non-NULL, the previous handling information for the signal
173 A signal-specific default action may be reset by
198 .Bl -tag -offset indent -width SA_RESETHANDXX
206 signal will be generated only when a child process exits,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
[all …]
/freebsd/sys/arm64/arm64/
H A Dnexus.c1 /*-
36 * this code implements the core resource managers for interrupt
46 #include <sys/interrupt.h>
85 "Force all devices to use non-posted device memory");
187 nexus_print_child(device_t bus, device_t child) in nexus_print_child() argument
191 retval += bus_print_child_header(bus, child); in nexus_print_child()
200 device_t child; in nexus_add_child() local
206 resource_list_init(&ndev->nx_resources); in nexus_add_child()
208 child = device_add_child_ordered(bus, order, name, unit); in nexus_add_child()
211 device_set_ivars(child, ndev); in nexus_add_child()
[all …]

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