Lines Matching +full:child +full:- +full:interrupt +full:- +full:base
5 using a queued mailbox interrupt mechanism. The IP block is external to the
8 interrupt configuration registers.
11 interrupt lines. An output interrupt line is routed to an interrupt controller
13 specific processor's interrupt controller. The interrupt line connections are
15 (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
16 programmable through a set of interrupt configuration registers, and have a rx
17 and tx interrupt source per h/w fifo. Communication between different processors
18 is achieved through the appropriate programming of the rx and tx interrupt
19 sources on the appropriate interrupt lines.
21 The number of h/w fifo queues and interrupt lines dictate the usable registers.
24 and interrupt lines between different instances. The interrupt lines can also be
25 routed to different processor sub-systems on DRA7xx as they are routed through
26 the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
28 into a single IP block present within the Main NavSS. The interrupt lines from
30 over a limited number of common interrupt output lines of an Interrupt Router.
32 but the number of clusters are smaller, and the interrupt output lines are
38 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
41 --------------------
42 - compatible: Should be one of the following,
43 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
44 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
45 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
47 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
48 "ti,am64-mailbox" for K3 AM64x SoCs
49 - reg: Contains the mailbox register address range (base
51 - interrupts: Contains the interrupt information for the mailbox
52 device. The format is dependent on which interrupt
54 - #mbox-cells: Common mailbox binding property to identify the number
57 - ti,mbox-num-users: Number of targets (processor devices) that the mailbox
58 device can interrupt
59 - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
61 SoC-specific Required properties:
62 ---------------------------------
65 - ti,hwmods: Name of the hwmod associated with the mailbox. This
67 is not defined as a child node of a corresponding sysc
71 - interrupt-parent: Should contain a phandle to the TI-SCI interrupt
73 the interrupt routes between the IP and the main GIC
76 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
78 Child Nodes:
80 A child node is used for representing the actual sub-mailbox device that is
82 Each child node should have a unique node name across all the different
86 --------------------
87 - ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
88 - ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
90 Sub-mailbox Descriptor Data
91 ---------------------------
92 Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
94 Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
95 (ti,mbox-tx) or for receiving (ti,mbox-rx)
96 Cell #2 (irq_id) - irq identifier index number to use from the parent's
99 multiple interrupt lines connected to the MPU processor.
100 Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
101 associated with generating a tx/rx fifo interrupt.
104 --------------------
105 - ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox
106 to send messages without triggering a Tx ready interrupt,
108 sub-mailboxes used to communicate with WkupM3 remote
115 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
118 the intended sub-mailbox child node to be used for communication. The equivalent
119 "mbox-names" property value can be used to give a name to the communication channel
124 --------
128 compatible = "ti,omap4-mailbox";
132 #mbox-cells = <1>;
133 ti,mbox-num-users = <3>;
134 ti,mbox-num-fifos = <8>;
136 ti,mbox-tx = <0 0 0>;
137 ti,mbox-rx = <1 0 0>;
140 ti,mbox-tx = <3 0 0>;
141 ti,mbox-rx = <2 0 0>;
153 compatible = "ti,omap4-mailbox";
157 #mbox-cells = <1>;
158 ti,mbox-num-users = <4>;
159 ti,mbox-num-fifos = <8>;
161 ti,mbox-tx = <0 0 0>;
162 ti,mbox-rx = <0 0 3>;
170 compatible = "ti,am654-mailbox";
172 #mbox-cells = <1>;
173 ti,mbox-num-users = <4>;
174 ti,mbox-num-fifos = <16>;
175 interrupt-parent = <&intr_main_navss>;
178 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
179 ti,mbox-tx = <1 0 0>;
180 ti,mbox-rx = <0 0 0>;