Lines Matching +full:child +full:- +full:interrupt +full:- +full:base

1 /*-
2  * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
66 u_int			 siba_get_intr_count(device_t dev, device_t child);
67 int			 siba_get_intr_ivec(device_t dev, device_t child,
75 int			 siba_init_dinfo(device_t dev, device_t child,
78 void			 siba_free_dinfo(device_t dev, device_t child,
128 #define	SIBA_CFG_RID_BASE	100			/**< base resource ID for SIBA_CFG* register allocations */
131 	    (_dinfo->core_id.core_info.core_idx * SIBA_MAX_CFG))
147 	uint32_t	am_base;	/**< base address. */
155 	uint32_t	sa_base;	/**< base address */
164 	uint32_t	cb_base;	/**< base address */
169 /** siba(4) backplane interrupt flag descriptor */
172 	int		rid;	/**< bus resource id, or -1 if unassigned */
177  * siba(4) per-core identification info.
182 								  *  the JEDEC-106 bhnd(4) vendor identifier. */
184 	bool			intr_en;			/**< if backplane interrupt distribution is enabled for this core */
185 	u_int			intr_flag;			/**< backplane interrupt flag # */
194  * siba(4) per-core PMU allocation state.
200 	SIBA_PMU_FIXED,		/**< If legacy fixed (no-op) PMU support should be used */
204  * siba(4) per-device info
207 	struct resource_list	 resources;			/**< per-core memory regions. */
211 	struct siba_intr	 intr;				/**< interrupt flag mapping, if any */
213 	struct bhnd_resource	*cfg_res[SIBA_MAX_CFG];		/**< bus-mapped config block registers */
214 	int			 cfg_rid[SIBA_MAX_CFG];		/**< bus-mapped config block resource IDs */
215 	siba_pmu_state		 pmu_state;			/**< per-core PMU state */
217 		void		*bhnd_info;	/**< if SIBA_PMU_BHND, bhnd(4)-managed per-core PMU info. */
222 /** siba(4) per-instance state */
230     mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
231 #define	SIBA_LOCK(sc)			mtx_lock(&(sc)->mtx)
232 #define	SIBA_UNLOCK(sc)			mtx_unlock(&(sc)->mtx)
233 #define	SIBA_LOCK_ASSERT(sc, what)	mtx_assert(&(sc)->mtx, what)
234 #define	SIBA_LOCK_DESTROY(sc)		mtx_destroy(&(sc)->mtx)