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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_pcs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define GMAC_AN_CTRL_RAN BIT(9) /* Restart Auto-Negotiation */
28 #define GMAC_AN_CTRL_ANE BIT(12) /* Auto-Negotiation Enable */
36 #define GMAC_AN_STATUS_ANA BIT(3) /* Auto-Negotiation Ability */
37 #define GMAC_AN_STATUS_ANC BIT(5) /* Auto-Negotiation Complete */
50 * dwmac_pcs_isr - TBI, RTBI, or SGMII PHY ISR
55 * Description: it is the ISR for PCS events: Auto-Negotiation Completed and
65 x->irq_pcs_ane_n++; in dwmac_pcs_isr()
71 x->irq_pcs_link_n++; in dwmac_pcs_isr()
80 * dwmac_ctrl_ane - To program the AN Control Register.
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * e1000e_get_bus_info_pcie - Get PCIe bus information
18 struct pci_dev *pdev = hw->adapter->pdev; in e1000e_get_bus_info_pcie()
19 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
20 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
24 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
27 bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW, in e1000e_get_bus_info_pcie()
31 mac->ops.set_lan_id(hw); in e1000e_get_bus_info_pcie()
37 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
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H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
62 struct e1000_phy_info *phy = &hw->phy; in e1000e_get_phy_id()
67 if (!phy->ops.read_reg) in e1000e_get_phy_id()
75 phy->id = (u32)(phy_id << 16); in e1000e_get_phy_id()
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in e1000e_get_phy_id()
82 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in e1000e_get_phy_id()
84 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) in e1000e_get_phy_id()
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_phy.c1 // SPDX-License-Identifier: GPL-2.0
8 * igc_check_reset_block - Check if PHY reset is blocked
26 * igc_get_phy_id - Retrieve the PHY ID and revision
34 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
42 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
44 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
48 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in igc_get_phy_id()
49 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in igc_get_phy_id()
56 * igc_phy_has_link - Polls PHY for link
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H A Digc_mac.c1 // SPDX-License-Identifier: GPL-2.0
11 * igc_disable_pcie_master - Disables PCI-express master access
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18 * Disables PCI-Express master access and verifies there are no pending
36 timeout--; in igc_disable_pcie_master()
41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING; in igc_disable_pcie_master()
50 * igc_init_rx_addrs - Initialize receive addresses
66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in igc_init_rx_addrs()
68 /* Zero out the other (rar_entry_count - 1) receive addresses */ in igc_init_rx_addrs()
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/linux/include/uapi/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
45 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
48 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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/linux/tools/testing/selftests/drivers/net/hw/lib/py/
H A Dlinkconfig.py
/linux/rust/kernel/net/phy/
H A Dreg.rs1 // SPDX-License-Identifier: GPL-2.0
45 fn read(&self, dev: &mut Device) -> Result<u16>; in read()
48 fn write(&self, dev: &mut Device, val: u16) -> Result; in write()
51 fn read_status(dev: &mut Device) -> Result<u16>; in read_status()
67 /// Auto-negotiation advertisement.
69 /// Auto-negotiation link partner base page ability.
71 /// Auto-negotiation expansion.
73 /// Auto-negotiation next page transmit.
75 /// Auto-negotiation link partner received next page.
77 /// Master-slave control.
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/linux/include/linux/
H A Dsmscphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define MII_LAN83C185_ISF_INT1 (1<<1) /* Auto-Negotiation Page Received */
12 #define MII_LAN83C185_ISF_INT3 (1<<3) /* Auto-Negotiation LP Ack */
15 #define MII_LAN83C185_ISF_INT6 (1<<6) /* Auto-Negotiation complete */
H A Dbrcmphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
94 #define MII_BCM54XX_EXP_SEL_WOL 0x0e00 /* Wake-on-LAN expansion select register */
111 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
212 /* 01010: Auto Power-Down */
231 /* 10011: SerDes 100-FX Control Register */
233 #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */
241 #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */
263 /* Top-MISC expansion registers */
275 #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
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/linux/drivers/net/phy/
H A Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "mdio-open-alliance.h"
12 #include "phylib-internal.h"
15 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
22 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
27 phydev->pma_extable = val; in genphy_c45_baset1_able()
30 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
34 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
49 * genphy_c45_pma_resume - wakes up the PMA module
55 return -EOPNOTSUPP; in genphy_c45_pma_resume()
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-helper-sgmii.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
63 * auto negotiation. The result of this function may not match
64 * Octeon's link config if auto negotiation has changed since
75 * function does not influence auto negotiation at the PHY level.
H A Dcvmx-helper-spi.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
60 * auto negotiation. The result of this function may not match
61 * Octeon's link config if auto negotiation has changed since
72 * function does not influence auto negotiation at the PHY level.
H A Dcvmx-helper-xaui.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
63 * auto negotiation. The result of this function may not match
64 * Octeon's link config if auto negotiation has changed since
75 * function does not influence auto negotiation at the PHY level.
H A Dcvmx-helper-rgmii.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
43 * Returns Number of RGMII/GMII/MII ports (0-4).
69 * auto negotiation. The result of this function may not match
70 * Octeon's link config if auto negotiation has changed since
81 * function does not influence auto negotiation at the PHY level.
H A Dcvmx-helper.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
37 #include <asm/octeon/cvmx-config.h>
38 #include <asm/octeon/cvmx-fpa.h>
39 #include <asm/octeon/cvmx-wqe.h>
64 #include <asm/octeon/cvmx-helper-errata.h>
65 #include <asm/octeon/cvmx-helper-loop.h>
66 #include <asm/octeon/cvmx-helper-npi.h>
67 #include <asm/octeon/cvmx-helper-rgmii.h>
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/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
18 #include "xgbe-common.h"
23 if (!pdata->phy_if.phy_impl.module_eeprom) in xgbe_phy_module_eeprom()
24 return -ENXIO; in xgbe_phy_module_eeprom()
26 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data); in xgbe_phy_module_eeprom()
32 if (!pdata->phy_if.phy_impl.module_info) in xgbe_phy_module_info()
33 return -ENXIO; in xgbe_phy_module_info()
35 return pdata->phy_if.phy_impl.module_info(pdata, modinfo); in xgbe_phy_module_info()
90 switch (pdata->an_mode) { in xgbe_an_enable_interrupts()
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/linux/Documentation/networking/device_drivers/ethernet/netronome/
H A Dnfp.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
14 - `Overview`_
15 - `Acquiring Firmware`_
16 - `Devlink Info`_
17 - `Configure Device`_
18 - `Statistics`_
25 are also incorporated in the companies' family of Agilio SmartNICs. The SR-IOV
35 Firmware files on the host filesystem contain card type (`AMDA-*` string), media
40 `linux-firmware.git` repository.
46 -----------------
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/linux/Documentation/networking/device_drivers/ethernet/intel/
H A De1000.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
50 -------
54 :Valid Range: 0x01-0x0F, 0x20-0x2F
57 This parameter is a bit-mask that specifies the speed and duplex settings
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-gmxx-defs.h>
41 #include <asm/octeon/cvmx-pcsx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
54 const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; in __cvmx_helper_sgmii_hardware_init_one_time()
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H A Dcvmx-helper-spi.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
35 #include <asm/octeon/cvmx-spi.h>
36 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-pip-defs.h>
39 #include <asm/octeon/cvmx-pko-defs.h>
40 #include <asm/octeon/cvmx-spxx-defs.h>
41 #include <asm/octeon/cvmx-stxx-defs.h>
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/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.c1 // SPDX-License-Identifier: GPL-2.0
43 * PARAMS: cphy - Pointer to PHY instance data.
45 * RETURN: 0 - Successful reset.
46 * -1 - Timeout.
60 } while (ctl && --time_out); in mv88e1xxx_reset()
62 return ctl ? -1 : 0; in mv88e1xxx_reset()
72 if (t1_is_asic(cphy->adapter)) { in mv88e1xxx_interrupt_enable()
75 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); in mv88e1xxx_interrupt_enable()
77 if (is_T2(cphy->adapter)) in mv88e1xxx_interrupt_enable()
79 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); in mv88e1xxx_interrupt_enable()
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/linux/drivers/net/ethernet/dec/tulip/
H A Dpnic2.c5 Written/copyright 1994-2001 by Donald Becker.
15 /* Understanding the PNIC_II - everything is this file is based
24 * -----
25 * Bit 24 - SCR
26 * Bit 23 - PCS
27 * Bit 22 - TTM (Trasmit Threshold Mode)
28 * Bit 18 - Port Select
29 * Bit 13 - Start - 1, Stop - 0 Transmissions
30 * Bit 11:10 - Loop Back Operation Mode
31 * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set)
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
31 * igb_check_reset_block - Check if PHY reset is blocked
48 * igb_get_phy_id - Retrieve the PHY ID and revision
56 struct e1000_phy_info *phy = &hw->phy; in igb_get_phy_id()
61 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) in igb_get_phy_id()
62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_get_phy_id()
64 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igb_get_phy_id()
68 phy->id = (u32)(phy_id << 16); in igb_get_phy_id()
70 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igb_get_phy_id()
[all …]
H A De1000_mac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
19 * igb_get_bus_info_pcie - Get PCIe bus information
28 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
33 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
39 bus->width = e1000_bus_width_unknown; in igb_get_bus_info_pcie()
40 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
44 bus->speed = e1000_bus_speed_2500; in igb_get_bus_info_pcie()
47 bus->speed = e1000_bus_speed_5000; in igb_get_bus_info_pcie()
50 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
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