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/linux/drivers/clk/renesas/
H A Drzg2l-cpg.h151 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
152 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
153 #define DEF_G3L_PLL(_name, _id, _parent, _conf, _default_rate) \ argument
154 DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLL, .parent = _parent, .conf = _conf, \
156 #define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \ argument
157 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \
163 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ argument
164 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
167 #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ argument
168 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
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H A Dr9a09g077-cpg.c76 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ argument
77 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_DIV, .conf = _conf, \
79 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \ argument
80 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \
83 #define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \ argument
84 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf = _conf, \
/linux/drivers/regulator/
H A Dpv88060-regulator.h48 /* PV88060_REG_SW1/2/3/4/5_CONF */
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dti,dra7-iodelay.yaml36 ^.*_conf$: