1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r9a09g077 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 * 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk-provider.h> 11 #include <linux/device.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 15 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> 16 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h> 17 #include "renesas-cpg-mssr.h" 18 19 #define RZT2H_REG_BLOCK_SHIFT 11 20 #define RZT2H_REG_OFFSET_MASK GENMASK(10, 0) 21 #define RZT2H_REG_CONF(block, offset) (((block) << RZT2H_REG_BLOCK_SHIFT) | \ 22 ((offset) & RZT2H_REG_OFFSET_MASK)) 23 24 #define RZT2H_REG_BLOCK(x) ((x) >> RZT2H_REG_BLOCK_SHIFT) 25 #define RZT2H_REG_OFFSET(x) ((x) & RZT2H_REG_OFFSET_MASK) 26 27 #define SCKCR RZT2H_REG_CONF(0, 0x00) 28 #define SCKCR2 RZT2H_REG_CONF(1, 0x04) 29 #define SCKCR3 RZT2H_REG_CONF(0, 0x08) 30 31 #define OFFSET_MASK GENMASK(31, 20) 32 #define SHIFT_MASK GENMASK(19, 12) 33 #define WIDTH_MASK GENMASK(11, 8) 34 35 #define CONF_PACK(offset, shift, width) \ 36 (FIELD_PREP_CONST(OFFSET_MASK, (offset)) | \ 37 FIELD_PREP_CONST(SHIFT_MASK, (shift)) | \ 38 FIELD_PREP_CONST(WIDTH_MASK, (width))) 39 40 #define GET_SHIFT(val) FIELD_GET(SHIFT_MASK, val) 41 #define GET_WIDTH(val) FIELD_GET(WIDTH_MASK, val) 42 #define GET_REG_OFFSET(val) FIELD_GET(OFFSET_MASK, val) 43 44 #define DIVCA55C0 CONF_PACK(SCKCR2, 8, 1) 45 #define DIVCA55C1 CONF_PACK(SCKCR2, 9, 1) 46 #define DIVCA55C2 CONF_PACK(SCKCR2, 10, 1) 47 #define DIVCA55C3 CONF_PACK(SCKCR2, 11, 1) 48 #define DIVCA55S CONF_PACK(SCKCR2, 12, 1) 49 50 #define DIVSCI0ASYNC CONF_PACK(SCKCR3, 6, 2) 51 52 #define SEL_PLL CONF_PACK(SCKCR, 22, 1) 53 54 55 enum rzt2h_clk_types { 56 CLK_TYPE_RZT2H_DIV = CLK_TYPE_CUSTOM, /* Clock with divider */ 57 CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */ 58 }; 59 60 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ 61 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_DIV, .conf = _conf, \ 62 .parent = _parent, .dtable = _dtable, .flag = 0) 63 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \ 64 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \ 65 .parent_names = _parent_names, .num_parents = _num_parents, \ 66 .flag = 0, .mux_flags = _mux_flags) 67 68 enum clk_ids { 69 /* Core Clock Outputs exported to DT */ 70 LAST_DT_CORE_CLK = R9A09G077_SDHI_CLKHS, 71 72 /* External Input Clocks */ 73 CLK_EXTAL, 74 75 /* Internal Core Clocks */ 76 CLK_LOCO, 77 CLK_PLL0, 78 CLK_PLL1, 79 CLK_PLL2, 80 CLK_PLL4, 81 CLK_SEL_CLK_PLL0, 82 CLK_SEL_CLK_PLL1, 83 CLK_SEL_CLK_PLL2, 84 CLK_SEL_CLK_PLL4, 85 CLK_PLL4D1, 86 CLK_SCI0ASYNC, 87 88 /* Module Clocks */ 89 MOD_CLK_BASE, 90 }; 91 92 static const struct clk_div_table dtable_1_2[] = { 93 {0, 2}, 94 {1, 1}, 95 {0, 0}, 96 }; 97 98 static const struct clk_div_table dtable_24_25_30_32[] = { 99 {0, 32}, 100 {1, 30}, 101 {2, 25}, 102 {3, 24}, 103 {0, 0}, 104 }; 105 106 /* Mux clock tables */ 107 108 static const char * const sel_clk_pll0[] = { ".loco", ".pll0" }; 109 static const char * const sel_clk_pll1[] = { ".loco", ".pll1" }; 110 static const char * const sel_clk_pll2[] = { ".loco", ".pll2" }; 111 static const char * const sel_clk_pll4[] = { ".loco", ".pll4" }; 112 113 static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { 114 /* External Clock Inputs */ 115 DEF_INPUT("extal", CLK_EXTAL), 116 117 /* Internal Core Clocks */ 118 DEF_RATE(".loco", CLK_LOCO, 1000 * 1000), 119 DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 1, 48), 120 DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40), 121 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 1, 32), 122 DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96), 123 124 DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL, 125 sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY), 126 DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL, 127 sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY), 128 DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL, 129 sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY), 130 DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL, 131 sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY), 132 133 DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1), 134 DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC, 135 dtable_24_25_30_32), 136 137 /* Core output clk */ 138 DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0, 139 dtable_1_2), 140 DEF_DIV("CA55C1", R9A09G077_CLK_CA55C1, CLK_SEL_CLK_PLL0, DIVCA55C1, 141 dtable_1_2), 142 DEF_DIV("CA55C2", R9A09G077_CLK_CA55C2, CLK_SEL_CLK_PLL0, DIVCA55C2, 143 dtable_1_2), 144 DEF_DIV("CA55C3", R9A09G077_CLK_CA55C3, CLK_SEL_CLK_PLL0, DIVCA55C3, 145 dtable_1_2), 146 DEF_DIV("CA55S", R9A09G077_CLK_CA55S, CLK_SEL_CLK_PLL0, DIVCA55S, 147 dtable_1_2), 148 DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1), 149 DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1), 150 DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1), 151 DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1), 152 DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1), 153 }; 154 155 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = { 156 DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC), 157 DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL), 158 DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL), 159 DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL), 160 DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM), 161 DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM), 162 }; 163 164 static struct clk * __init 165 r9a09g077_cpg_div_clk_register(struct device *dev, 166 const struct cpg_core_clk *core, 167 void __iomem *addr, struct cpg_mssr_pub *pub) 168 { 169 const struct clk *parent; 170 const char *parent_name; 171 struct clk_hw *clk_hw; 172 173 parent = pub->clks[core->parent]; 174 if (IS_ERR(parent)) 175 return ERR_CAST(parent); 176 177 parent_name = __clk_get_name(parent); 178 179 if (core->dtable) 180 clk_hw = clk_hw_register_divider_table(dev, core->name, 181 parent_name, 0, 182 addr, 183 GET_SHIFT(core->conf), 184 GET_WIDTH(core->conf), 185 core->flag, 186 core->dtable, 187 &pub->rmw_lock); 188 else 189 clk_hw = clk_hw_register_divider(dev, core->name, 190 parent_name, 0, 191 addr, 192 GET_SHIFT(core->conf), 193 GET_WIDTH(core->conf), 194 core->flag, &pub->rmw_lock); 195 196 if (IS_ERR(clk_hw)) 197 return ERR_CAST(clk_hw); 198 199 return clk_hw->clk; 200 201 } 202 203 static struct clk * __init 204 r9a09g077_cpg_mux_clk_register(struct device *dev, 205 const struct cpg_core_clk *core, 206 void __iomem *addr, struct cpg_mssr_pub *pub) 207 { 208 struct clk_hw *clk_hw; 209 210 clk_hw = devm_clk_hw_register_mux(dev, core->name, 211 core->parent_names, core->num_parents, 212 core->flag, 213 addr, 214 GET_SHIFT(core->conf), 215 GET_WIDTH(core->conf), 216 core->mux_flags, &pub->rmw_lock); 217 if (IS_ERR(clk_hw)) 218 return ERR_CAST(clk_hw); 219 220 return clk_hw->clk; 221 } 222 223 static struct clk * __init 224 r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, 225 const struct cpg_mssr_info *info, 226 struct cpg_mssr_pub *pub) 227 { 228 u32 offset = GET_REG_OFFSET(core->conf); 229 void __iomem *base = RZT2H_REG_BLOCK(offset) ? pub->base1 : pub->base0; 230 void __iomem *addr = base + RZT2H_REG_OFFSET(offset); 231 232 switch (core->type) { 233 case CLK_TYPE_RZT2H_DIV: 234 return r9a09g077_cpg_div_clk_register(dev, core, addr, pub); 235 case CLK_TYPE_RZT2H_MUX: 236 return r9a09g077_cpg_mux_clk_register(dev, core, addr, pub); 237 default: 238 return ERR_PTR(-EINVAL); 239 } 240 } 241 242 const struct cpg_mssr_info r9a09g077_cpg_mssr_info = { 243 /* Core Clocks */ 244 .core_clks = r9a09g077_core_clks, 245 .num_core_clks = ARRAY_SIZE(r9a09g077_core_clks), 246 .last_dt_core_clk = LAST_DT_CORE_CLK, 247 .num_total_core_clks = MOD_CLK_BASE, 248 249 /* Module Clocks */ 250 .mod_clks = r9a09g077_mod_clks, 251 .num_mod_clks = ARRAY_SIZE(r9a09g077_mod_clks), 252 .num_hw_mod_clks = 14 * 32, 253 254 .reg_layout = CLK_REG_LAYOUT_RZ_T2H, 255 .cpg_clk_register = r9a09g077_cpg_clk_register, 256 }; 257