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Searched +full:tri +full:- +full:state (Results 1 – 25 of 195) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A D	AggressiveAntiDepBreaker.cpp	1 //===- AggressiveAntiDepBreaker.cpp - Anti-dep breaker --------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 // implements register anti-dependence breaking during post-RA 11 // scheduling. It attempts to break all anti-dependencies within a 14 //===----------------------------------------------------------------------===// 41 #define DEBUG_TYPE "post-RA-sched" 45 DebugDiv("agg-antidep-debugdiv", 46 cl::desc("Debug control for aggressive anti-dep breaker"), 50 DebugMod("agg-antidep-debugmod", [all …]
H A D	CriticalAntiDepBreaker.cpp	1 //===- CriticalAntiDepBreaker.cpp - Anti-dep breaker ----------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 // implements register anti-dependence breaking along a blocks 11 // critical path during post-RA scheduler. 13 //===----------------------------------------------------------------------===// 39 #define DEBUG_TYPE "post-RA-sched" 44 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker() 45 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker() 46 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {} in CriticalAntiDepBreaker() [all …]
H A D	RegAllocFast.cpp	1 //===- RegAllocFast.cpp - A fast register allocator for debug code --------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===// 58 static cl::opt<bool> IgnoreMissingDefs("rafast-ignore-missing-defs", 96 Index = It->second; in getIndex() 112 while (Start != CurMBB->begin() && in getIndex() 114 --Start; in getIndex() 117 while (End != CurMBB->end() && !Instr2PosIndex.count(&(End))) { in getIndex() 125 Start == CurMBB->begin() ? 0 : Instr2PosIndex.at(&std::prev(Start)); in getIndex() [all …]
H A D	FixupStatepointCallerSaved.cpp	1 //===-- FixupStatepointCallerSaved.cpp - Fixup caller saved registers ----===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 21 //===----------------------------------------------------------------------===// 35 #define DEBUG_TYPE "fixup-statepoint-caller-saved" 41 "fixup-scs-extend-slot-size", cl::Hidden, cl::init(false), 46 "fixup-allow-gcptr-in-csr", cl::Hidden, cl::init(false), 50 "fixup-scs-enable-copy-propagation", cl::Hidden, cl::init(true), 56 "fixup-max-csr-statepoints", cl::Hidden, 92 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) { in getRegisterSize() argument [all …]
H A D	CallingConvLower.cpp	1 //===-- CallingConvLower.cpp - Calling Conventions ------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 32 TRI(*MF.getSubtarget().getRegisterInfo()), Locs(Locs), Context(Context), in CCState() 39 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState() 55 MF.getSubtarget().getTargetLowering()->HandleByVal(this, Size, Alignment); in HandleByVal() 63 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) in MarkAllocated() 68 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) in MarkUnallocated() 77 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg() [all …]
H A D	MachineVerifier.cpp	1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 19 // The machine code verifier is enabled with the command-line option 20 // -verify-machineinstrs. 21 //===----------------------------------------------------------------------===// 116 const TargetRegisterInfo *TRI = nullptr; member 144 // Add Reg and any sub-registers to RV 148 append_range(RV, TRI->subregs(Reg.asMCReg())); in addRegWithSubRegs() 207 // Live-out registers are either in regsLiveOut or vregsPassed. [all …]
H A D	RegisterPressure.cpp	1 //===- RegisterPressure.cpp - Dynamic Register Pressure -------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 30 #include "llvm/Config/llvm-config.h" 75 CurrSetPressure[PSetI] -= Weight; in decreaseSetPressure() 82 const TargetRegisterInfo TRI) { in dumpRegSetPressure() argument 86 dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << '\n'; in dumpRegSetPressure() 95 void RegisterPressure::dump(const TargetRegisterInfo *TRI) const { in dump() 97 dumpRegSetPressure(MaxSetPressure, TRI); in dump() [all …]
H A D	AggressiveAntiDepBreaker.h	`1 //==- llvm/CodeGen/AggressiveAntiDepBreaker.h - Anti-Dep Support -- C++ --==// 5 // SPDX-License-Identifier: Apache-2. 121 const TargetRegisterInfo TRI; global() variable 129 AggressiveAntiDepState State = nullptr; global() variable [all...]`
H A D	ProcessImplicitDefs.cpp	1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 31 const TargetRegisterInfo *TRI = nullptr; member in __anonb70e92d00111::ProcessImplicitDefs 70 if (!MI->isCopyLike() && in canTurnIntoImplicitDef() 71 !MI->isInsertSubreg() && in canTurnIntoImplicitDef() 72 !MI->isRegSequence() && in canTurnIntoImplicitDef() 73 !MI->isPHI()) in canTurnIntoImplicitDef() 75 for (const MachineOperand &MO : MI->all_uses()) in canTurnIntoImplicitDef() 83 Register Reg = MI->getOperand(0).getReg(); in processImplicitDef() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A D	GCNHazardRecognizer.cpp	1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls ------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 43 MFMAPaddingRatio("amdgpu-mfma-padding-ratio", cl::init(0), cl::Hidden, 47 //===----------------------------------------------------------------------===// 49 //===----------------------------------------------------------------------===// 60 TRI(TII.getRegisterInfo()), in GCNHazardRecognizer() 61 ClauseUses(TRI.getNumRegUnits()), in GCNHazardRecognizer() 62 ClauseDefs(TRI.getNumRegUnits()) { in GCNHazardRecognizer() [all …]
H A D	AMDGPUInsertDelayAlu.cpp	1 //===- AMDGPUInsertDelayAlu.cpp - Insert s_delay_alu instructions ---------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 22 #define DEBUG_TYPE "amdgpu-insert-delay-alu" 31 const TargetRegisterInfo *TRI; member in __anon39c000570111::AMDGPUInsertDelayAlu 74 // regunit. In straight-line code there will only be one such instruction, but 76 // to represent the union of the worst-case delays of each type. 78 // One larger than the maximum number of (non-TRANS) VALU instructions we 90 // If it was written by a (non-TRANS) VALU, remember how many clock cycles [all …]
H A D	SIWholeQuadMode.cpp	1 //===-- SIWholeQuadMode.cpp - enter and suspend whole quad mode -----------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 /// This pass adds instructions to enable whole quad mode (strict or non-strict) 16 /// non-strict WQM inactive lanes may control flow decisions. 37 /// S_OR_SAVEEXEC_B64 Tmp, -1 63 /// (2) when entire regions (e.g. if-else blocks or entire loops) only 64 /// consist of exact and don't-care instructions, the switch only has to 68 //===----------------------------------------------------------------------===// 87 #define DEBUG_TYPE "si-wqm" [all …]
H A D	SIFormMemoryClauses.cpp	1 //===-- SIFormMemoryClauses.cpp -------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 /// implicit-def early-clobber operands throughout the soft clause. 15 //===----------------------------------------------------------------------===// 24 #define DEBUG_TYPE "si-form-memory-clauses" 29 MaxClause("amdgpu-max-memory-clause", cl::Hidden, cl::init(15), 71 const SIRegisterInfo *TRI; member in __anon72ebc0cc0111::SIFormMemoryClauses 106 // thus there is nothing to set early-clobber. 176 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg()); in canBundle() [all …]
H A D	GCNNSAReassign.cpp	1 //===-- GCNNSAReassign.cpp - Reassign registers in NSA instructions -------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 /// \brief Try to reassign registers on GFX10+ from non-sequential to sequential 14 //===----------------------------------------------------------------------===// 29 #define DEBUG_TYPE "amdgpu-nsa-reassign" 32 "Number of NSA instructions with non-sequential address found"); 62 NON_CONTIGUOUS, // NSA with non-sequential address which we can try 71 const SIRegisterInfo *TRI; member in __anond94b4ce90111::GCNNSAReassign 114 if (VRM->hasPhys(Intervals[N]->reg())) in tryAssignRegisters() [all …]
H A D	SIFixSGPRCopies.cpp	1 //===- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies ---------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 65 //===----------------------------------------------------------------------===// 77 #define DEBUG_TYPE "si-fix-sgpr-copies" 80 "amdgpu-enable-merge-m0", 100 // Current score state. To speedup selection V2SCopyInfos for processing 135 const SIRegisterInfo *TRI; member in __anon8637e2150111::SIFixSGPRCopies 190 const SIRegisterInfo &TRI, in getCopyRegClasses() argument 197 : TRI.getPhysRegBaseClass(SrcReg); in getCopyRegClasses() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A D	M68kCollapseMOVEMPass.cpp	1 //===-- M68kCollapseMOVEMPass.cpp - Expand MOVEM pass ------------ C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 15 //===----------------------------------------------------------------------===// 32 #define DEBUG_TYPE "m68k-collapse-movem" 114 } else if (Type == Descending && O == Start - 4) { in update() 115 Start -= 4; in update() 163 const M68kRegisterInfo *TRI; member in __anon143e10ef0111::M68kCollapseMOVEM 169 void Finish(MachineBasicBlock &MBB, MOVEMState &State) { in Finish() argument 170 auto MI = State.begin(); in Finish() [all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A D	pinctrl-bindings.txt	4 such as pull-up/down, tri-state, drive-strength etc are designated as pin 15 need to reconfigure pins at run-time, for example to tri-state pins when the 21 for client device device tree nodes to map those state names to the pin 25 For example, a pin controller may set up its own "active" state when the 35 For each client device individually, every pin state is assigned an integer 36 ID. These numbers start at 0, and are contiguous. For each state ID, a unique 37 property exists to define the pin configuration. Each state may also be 42 defined in its device tree node, and whether to define the set of state 43 IDs that must be provided, or whether to define the set of state names that 47 pinctrl-0: List of phandles, each pointing at a pin configuration [all …]
H A D	nvidia,tegra20-pinmux.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmu [all...]`
H A D	nvidia,tegra20-pinmux.txt	4 - compatible: "nvidia,tegra20-pinmux" 5 - reg: Should contain the register physical address and length for each of 6 the tri-state, mux, pull-up/down, and pad control register sets. 8 Please refer to pinctrl-bindings.txt in this directory for details of the 16 parameters, such as pull-up, tristate, drive strength, etc. 30 Required subnode-properties: 31 - nvidia,pins : An array of strings. Each string contains the name of a pin or 34 Optional subnode-properties: 35 - nvidia,function: A string containing the name of the function to mux to the 38 - nvidia,pull: Integer, representing the pull-down/up to apply to the pin. [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A D	AArch64CallLowering.cpp	1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===// 51 #define DEBUG_TYPE "aarch64-call-lowering" 64 // hack because the DAG calls the assignment function with pre-legalized in applyStackPassedSmallTypeDAGHack() 93 CCState &State) override { in assignArg() 96 LocInfo, Info, Flags, State); in assignArg() 119 CCState &State) override { in assignArg() 120 const Function &F = State.getMachineFunction().getFunction(); in assignArg() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86SpeculativeLoadHardening.cpp	1 //====- X86SpeculativeLoadHardening.cpp - A Spectre v1 mitigation ---------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 17 /// https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html 20 //===----------------------------------------------------------------------===// 63 #define PASS_KEY "x86-slh" 71 "Number of post-load register values hardened"); 78 "x86-speculative-load-hardening", 83 PASS_KEY "-lfence", 90 PASS_KEY "-post-load", [all …]
H A D	X86CallingConv.cpp	1 //=== X86CallingConv.cpp - X86 Custom Calling Convention Impl -- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===- 30 CC_X86_32_RegCall_Assign2Regs(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State) CC_X86_32_RegCall_Assign2Regs() argument 94 CC_X86_VectorCallAssignRegister(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State) CC_X86_VectorCallAssignRegister() argument 130 CC_X86_64_VectorCall(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State) CC_X86_64_VectorCall() argument 165 const TargetRegisterInfo *TRI = CC_X86_64_VectorCall() local 190 CC_X86_32_VectorCall(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State) CC_X86_32_VectorCall() argument 239 CC_X86_32_MCUInReg(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State) CC_X86_32_MCUInReg() argument 299 CC_X86_Intr(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State) CC_X86_Intr() argument 335 CC_X86_64_Pointer(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State) CC_X86_64_Pointer() argument [all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A D	ResourcePriorityQueue.cpp	1 //===- ResourcePriorityQueue.cpp - A DFA-oriented priority queue -- C++ --==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 // SchedulingPriorityQueue that prioritizes instructions using DFA state to 13 // The scheduler is basically a top-down adaptable list scheduler with DFA 15 // DFA is queried as a state machine to model "packets/bundles" during 19 //===----------------------------------------------------------------------===// 36 DisableDFASched("disable-dfa-sched", cl::Hidden, 40 "dfa-sched-reg-pressure-threshold", cl::Hidden, cl::init(5), 41 cl::desc("Track reg pressure and switch priority to in-depth")); [all …]
H A D	ScheduleDAGRRList.cpp	1 //===- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler ------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This implements bottom-up and top-down register pressure reduction list 15 //===----------------------------------------------------------------------===// 39 #include "llvm/Config/llvm-config.h" 62 #define DEBUG_TYPE "pre-RA-sched" 70 burrListDAGScheduler("list-burr", 71 "Bottom-up register reduction list scheduling", 76 "Similar to list-burr but schedules in source " [all …]
/freebsd/contrib/libcxxrt/
H A D	guard.cc	2 * Copyright 2010-2012 PathScale, Inc. All rights reserved. 29 * guard.cc: Functions for thread-safe static initialisation. 37 * Statics that require initialisation are protected by a 64-bit value. Any 38 * platform that can do 32-bit atomic test and set operations can use this 39 * value as a low-overhead lock. Because statics (in most sane code) are 57 // x86 and ARM are the most common little-endian CPUs, so let's have a 66 * The Itanium C++ ABI defines guard words that are 64-bit (32-bit on AArch32) 71 * On many 32-bit platforms, 64-bit atomics are unavailable (or slow) and so we 72 * treat the two halves of the 64-bit word as independent values and establish 74 * lock word is in the locked state. This means that we can do double-checked [all …]

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