1 //===-- GCNNSAReassign.cpp - Reassign registers in NSA instructions -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// \brief Try to reassign registers on GFX10+ from non-sequential to sequential
14 //===----------------------------------------------------------------------===//
29 #define DEBUG_TYPE "amdgpu-nsa-reassign"
32           "Number of NSA instructions with non-sequential address found");
62     NON_CONTIGUOUS, // NSA with non-sequential address which we can try
71   const SIRegisterInfo *TRI;  member in __anond94b4ce90111::GCNNSAReassign
114     if (VRM->hasPhys(Intervals[N]->reg()))  in tryAssignRegisters()
115       LRM->unassign(*Intervals[N]);  in tryAssignRegisters()
118     if (LRM->checkInterference(*Intervals[N], MCRegister::from(StartReg + N)))  in tryAssignRegisters()
122     LRM->assign(*Intervals[N], MCRegister::from(StartReg + N));  in tryAssignRegisters()
130     if (!MRI->isAllocatable(Reg))  in canAssign()
134       if (TRI->isSubRegisterEq(Reg, CSRegs[I]) &&  in canAssign()
135           !LRM->isPhysRegUsed(CSRegs[I]))  in canAssign()
148   unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0;  in scavengeRegs()
167   switch (Info->MIMGEncoding) {  in CheckNSA()
180   for (unsigned I = 0; I < Info->VAddrOperands; ++I) {  in CheckNSA()
183     if (Reg.isPhysical() || !VRM->isAssignedReg(Reg))  in CheckNSA()
186     Register PhysReg = VRM->getPhys(Reg);  in CheckNSA()
201       if (TRI->getRegSizeInBits(*MRI->getRegClass(Reg)) != 32 || Op.getSubReg())  in CheckNSA()
205       // it in an inconsistent state, so we cannot call LRM::unassign().  in CheckNSA()
209       if (VRM->getPreSplitReg(Reg))  in CheckNSA()
212       const MachineInstr *Def = MRI->getUniqueVRegDef(Reg);  in CheckNSA()
214       if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)  in CheckNSA()
217       for (auto U : MRI->use_nodbg_operands(Reg)) {  in CheckNSA()
221         if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)  in CheckNSA()
225       if (!LIS->hasInterval(Reg))  in CheckNSA()
240   if (!ST->hasNSAEncoding() || !ST->hasNonNSAEncoding())  in runOnMachineFunction()
244   TRI = ST->getRegisterInfo();  in runOnMachineFunction()
250   MaxNumVGPRs = ST->getMaxNumVGPRs(MF);  in runOnMachineFunction()
251   MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(MFI->getOccupancy()), MaxNumVGPRs);  in runOnMachineFunction()
252   CSRegs = MRI->getCalleeSavedRegs();  in runOnMachineFunction()
285     const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI->getOpcode());  in runOnMachineFunction()
287       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::vaddr0);  in runOnMachineFunction()
292     for (unsigned I = 0; I < Info->VAddrOperands; ++I) {  in runOnMachineFunction()
293       const MachineOperand &Op = MI->getOperand(VAddr0Idx + I);  in runOnMachineFunction()
295       LiveInterval *LI = &LIS->getInterval(Reg);  in runOnMachineFunction()
302       OrigRegs.push_back(VRM->getPhys(Reg));  in runOnMachineFunction()
303       if (LI->empty()) {  in runOnMachineFunction()
307           MinInd = MaxInd = LIS->getInstructionIndex(*MI);  in runOnMachineFunction()
310       MinInd = I != 0 ? std::min(MinInd, LI->beginIndex()) : LI->beginIndex();  in runOnMachineFunction()
311       MaxInd = I != 0 ? std::max(MaxInd, LI->endIndex()) : LI->endIndex();  in runOnMachineFunction()
321                << " " << llvm::printReg((VRM->getPhys(LI->reg())), TRI);  in runOnMachineFunction()
327       if (VRM->hasPhys(Intervals.back()->reg())) // Did not change allocation.  in runOnMachineFunction()
333                                   return LIS->getInstructionIndex(*C.first) < I;  in runOnMachineFunction()
336               LIS->getInstructionIndex(*I->first) < MaxInd; ++I) {  in runOnMachineFunction()
337         if (I->second && CheckNSA(*I->first, true) < NSA_Status::CONTIGUOUS) {  in runOnMachineFunction()
339           LLVM_DEBUG(dbgs() << "\tNSA conversion conflict with " << *I->first);  in runOnMachineFunction()
345       for (unsigned I = 0; I < Info->VAddrOperands; ++I)  in runOnMachineFunction()
346         if (VRM->hasPhys(Intervals[I]->reg()))  in runOnMachineFunction()
347           LRM->unassign(*Intervals[I]);  in runOnMachineFunction()
349       for (unsigned I = 0; I < Info->VAddrOperands; ++I)  in runOnMachineFunction()
350         LRM->assign(*Intervals[I], OrigRegs[I]);  in runOnMachineFunction()
359                << llvm::printReg((VRM->getPhys(Intervals.front()->reg())), TRI)  in runOnMachineFunction()
361                << llvm::printReg((VRM->getPhys(Intervals.back()->reg())), TRI)  in runOnMachineFunction()