Lines Matching +full:tri +full:- +full:state
1 //===- RegAllocFast.cpp - A fast register allocator for debug code --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
58 static cl::opt<bool> IgnoreMissingDefs("rafast-ignore-missing-defs",
96 Index = It->second; in getIndex()
112 while (Start != CurMBB->begin() && in getIndex()
114 --Start; in getIndex()
117 while (End != CurMBB->end() && !Instr2PosIndex.count(&*(End))) { in getIndex()
125 Start == CurMBB->begin() ? 0 : Instr2PosIndex.at(&*std::prev(Start)); in getIndex()
127 if (End == CurMBB->end()) in getIndex()
133 unsigned NumAvailableIndexes = EndIndex - LastIndex - 1; in getIndex()
137 // |<- S-1 -> MI <- S-1 -> MI <- A-S*D ->| in getIndex()
138 // There're S-1 available indexes between unassigned instruction and its in getIndex()
139 // predecessor. There're A-S*D available indexes between the last in getIndex()
142 // S-1 = A-S*D in getIndex()
148 // A-S*D >= 0 in getIndex()
182 : ShouldAllocateRegisterImpl(F), StackSlotForVirtReg(-1), in RegAllocFastImpl()
188 const TargetRegisterInfo *TRI = nullptr; member in __anon43a0a7eb0111::RegAllocFastImpl
232 /// State of a register unit.
238 /// A pre-assigned register has been assigned before register allocation
243 /// live-in to the basic block.
246 /// A register state may also be a virtual register number, indication
263 /// instruction "generation" in the remaining 31 bits -- this means, that if
284 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in markRegUsedInInstr()
299 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in isRegUsedInInstr()
308 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in markPhysRegUsedInInstr()
309 assert(UsedInInstr[Unit] <= InstrGen && "non-phys use before phys use?"); in markPhysRegUsedInInstr()
316 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in unmarkRegUsedInInstr()
446 return ShouldAllocateRegisterImpl(*TRI, *MRI, Reg); in shouldAllocateRegister()
450 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in setPhysRegState()
455 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in isPhysRegFree()
468 if (SS != -1) in getStackSpaceFor()
472 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
473 unsigned Size = TRI->getSpillSize(RC); in getStackSpaceFor()
474 Align Alignment = TRI->getSpillAlign(RC); in getStackSpaceFor()
475 int FrameIdx = MFI->CreateSpillStackObject(Size, Alignment); in getStackSpaceFor()
494 // Cannot be live-out if there are no successors. in mayLiveOut()
495 return !MBB->succ_empty(); in mayLiveOut()
502 if (MBB->isSuccessor(MBB)) { in mayLiveOut()
504 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveOut()
523 for (const MachineInstr &UseInst : MRI->use_nodbg_instructions(VirtReg)) { in mayLiveOut()
526 // Cannot be live-out if there are no successors. in mayLiveOut()
527 return !MBB->succ_empty(); in mayLiveOut()
547 return !MBB->pred_empty(); in mayLiveIn()
552 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveIn()
555 return !MBB->pred_empty(); in mayLiveIn()
567 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " in " in spill()
568 << printReg(AssignedReg, TRI)); in spill()
572 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
573 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI, in spill()
577 MachineBasicBlock::iterator FirstTerm = MBB->getFirstTerminator(); in spill()
586 SpilledOperandsMap[MO->getParent()].push_back(MO); in spill()
594 assert(NewDV->getParent() == MBB && "dangling parent pointer"); in spill()
603 MachineInstr *ClonedDV = MBB->getParent()->CloneMachineInstr(NewDV); in spill()
604 MBB->insert(FirstTerm, ClonedDV); in spill()
627 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " in reload()
628 << printReg(PhysReg, TRI) << '\n'); in reload()
630 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in reload()
631 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg); in reload()
643 if (I->isLabel()) { in getMBBBeginInsertionPoint()
649 if (!TII->isBasicBlockPrologue(*I)) in getMBBBeginInsertionPoint()
654 for (MachineOperand &MO : I->operands()) { in getMBBBeginInsertionPoint()
672 // Set state to live-in. This possibly overrides mappings to virtual in reloadAtBegin()
688 MCRegister FirstUnit = *TRI->regunits(PhysReg).begin(); in reloadAtBegin()
692 assert((&MBB != &MBB.getParent()->front() || IgnoreMissingDefs) && in reloadAtBegin()
708 /// implicit kills to MO->getParent() and invalidate MO.
729 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in displacePhysReg()
736 reload(ReloadBefore, VirtReg, LRI->PhysReg); in displacePhysReg()
738 setPhysRegState(LRI->PhysReg, regFree); in displacePhysReg()
739 LRI->PhysReg = 0; in displacePhysReg()
740 LRI->Reloaded = true; in displacePhysReg()
756 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':'); in freePhysReg()
758 MCRegister FirstUnit = *TRI->regunits(PhysReg).begin(); in freePhysReg()
770 LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n'); in freePhysReg()
771 setPhysRegState(LRI->PhysReg, regFree); in freePhysReg()
772 LRI->PhysReg = 0; in freePhysReg()
780 /// disabled - it can be allocated directly.
783 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in calcSpillCost()
788 LLVM_DEBUG(dbgs() << "Cannot spill pre-assigned " in calcSpillCost()
789 << printReg(PhysReg, TRI) << '\n'); in calcSpillCost()
792 bool SureSpill = StackSlotForVirtReg[VirtReg] != -1 || in calcSpillCost()
793 findLiveVirtReg(VirtReg)->LiveOut; in calcSpillCost()
808 SmallVectorImpl<MachineInstr *> &Dangling = UDBGValIter->second; in assignDanglingDebugValues()
810 assert(DbgValue->isDebugValue()); in assignDanglingDebugValues()
811 if (!DbgValue->hasDebugOperandForReg(VirtReg)) in assignDanglingDebugValues()
818 E = DbgValue->getIterator(); in assignDanglingDebugValues()
820 if (I->modifiesRegister(Reg, TRI) || --Limit == 0) { in assignDanglingDebugValues()
827 for (MachineOperand &MO : DbgValue->getDebugOperandsForReg(VirtReg)) { in assignDanglingDebugValues()
836 /// This method updates local state so that we know that PhysReg is the
842 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to " in assignVirtToPhysReg()
843 << printReg(PhysReg, TRI) << '\n'); in assignVirtToPhysReg()
862 MachineInstr *VRegDef = MRI->getUniqueVRegDef(Reg); in traceCopyChain()
865 Reg = VRegDef->getOperand(1).getReg(); in traceCopyChain()
876 for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) { in traceCopies()
896 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtReg()
898 << " in class " << TRI->getRegClassName(&RC) in allocVirtReg()
899 << " with hint " << printReg(Hint0, TRI) << '\n'); in allocVirtReg()
902 if (Hint0.isPhysical() && MRI->isAllocatable(Hint0) && RC.contains(Hint0) && in allocVirtReg()
906 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI) in allocVirtReg()
911 LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint0, TRI) in allocVirtReg()
920 if (Hint1.isPhysical() && MRI->isAllocatable(Hint1) && RC.contains(Hint1) && in allocVirtReg()
924 LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint1, TRI) in allocVirtReg()
929 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint1, TRI) in allocVirtReg()
940 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' '); in allocVirtReg()
955 Cost -= spillPrefBonus; in allocVirtReg()
989 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in allocVirtRegUndef()
990 PhysReg = LRI->PhysReg; in allocVirtRegUndef()
992 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtRegUndef()
1000 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
1009 /// \return true if MI's MachineOperands were re-arranged/invalidated.
1017 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg()
1019 LLVM_DEBUG(dbgs() << "Need new assignment for " << printReg(PrevReg, TRI) in defineLiveThroughVirtReg()
1022 LRI->PhysReg = 0; in defineLiveThroughVirtReg()
1026 LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to " in defineLiveThroughVirtReg()
1027 << printReg(PrevReg, TRI) << '\n'); in defineLiveThroughVirtReg()
1029 TII->get(TargetOpcode::COPY), PrevReg) in defineLiveThroughVirtReg()
1030 .addReg(LRI->PhysReg, llvm::RegState::Kill); in defineLiveThroughVirtReg()
1034 LRI->LastUse = &MI; in defineLiveThroughVirtReg()
1043 /// - It is a dead definition without any uses.
1044 /// - The value is live out and all uses are in different basic blocks.
1046 /// \return true if MI's MachineOperands were re-arranged/invalidated.
1059 LRI->LiveOut = true; in defineVirtReg()
1066 if (LRI->PhysReg == 0) { in defineVirtReg()
1070 if (LRI->Error) { in defineVirtReg()
1071 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in defineVirtReg()
1078 assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) && in defineVirtReg()
1080 LLVM_DEBUG(dbgs() << "In def of " << printReg(VirtReg, TRI) in defineVirtReg()
1082 << printReg(LRI->PhysReg, TRI) << '\n'); in defineVirtReg()
1085 MCPhysReg PhysReg = LRI->PhysReg; in defineVirtReg()
1086 if (LRI->Reloaded || LRI->LiveOut) { in defineVirtReg()
1090 LLVM_DEBUG(dbgs() << "Spill Reason: LO: " << LRI->LiveOut in defineVirtReg()
1091 << " RL: " << LRI->Reloaded << '\n'); in defineVirtReg()
1092 bool Kill = LRI->LastUse == nullptr; in defineVirtReg()
1093 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); in defineVirtReg()
1099 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in defineVirtReg()
1103 TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI, in defineVirtReg()
1104 &RC, TRI, VirtReg); in defineVirtReg()
1106 Succ->addLiveIn(PhysReg); in defineVirtReg()
1111 LRI->LastUse = nullptr; in defineVirtReg()
1113 LRI->LiveOut = false; in defineVirtReg()
1114 LRI->Reloaded = false; in defineVirtReg()
1124 /// \return true if MI's MachineOperands were re-arranged/invalidated.
1136 LRI->LiveOut = true; in useVirtReg()
1143 assert((!MO.isKill() || LRI->LastUse == &MI) && "Invalid kill flag"); in useVirtReg()
1147 if (LRI->PhysReg == 0) { in useVirtReg()
1161 if (LRI->Error) { in useVirtReg()
1162 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in useVirtReg()
1170 LRI->LastUse = &MI; in useVirtReg()
1173 BundleVirtRegsMap[VirtReg] = LRI->PhysReg; in useVirtReg()
1175 markRegUsedInInstr(LRI->PhysReg); in useVirtReg()
1176 return setPhysReg(MI, MO, LRI->PhysReg); in useVirtReg()
1180 /// \return true if MI's MachineOperands were re-arranged/invalidated.
1190 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
1201 MI.addRegisterKilled(PhysReg, TRI, true); in setPhysReg()
1202 // Conservatively assume implicit MOs were re-arranged in setPhysReg()
1206 // A <def,read-undef> of a sub-register requires an implicit def of the full in setPhysReg()
1210 MI.addRegisterDead(PhysReg, TRI, true); in setPhysReg()
1212 MI.addRegisterDefined(PhysReg, TRI); in setPhysReg()
1213 // Conservatively assume implicit MOs were re-arranged in setPhysReg()
1222 for (unsigned Unit = 1, UnitE = TRI->getNumRegUnits(); Unit != UnitE; in dumpState()
1228 dbgs() << " " << printRegUnit(Unit, TRI) << "[P]"; in dumpState()
1233 dbgs() << ' ' << printRegUnit(Unit, TRI) << '=' << printReg(VirtReg); in dumpState()
1236 if (I->LiveOut || I->Reloaded) { in dumpState()
1238 if (I->LiveOut) in dumpState()
1240 if (I->Reloaded) in dumpState()
1244 assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present"); in dumpState()
1257 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in dumpState()
1268 assert(RegClassDefCounts.size() == TRI->getNumRegClasses()); in addRegClassDefCounts()
1273 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts()
1274 for (unsigned RCIdx = 0, RCIdxEnd = TRI->getNumRegClasses(); in addRegClassDefCounts()
1276 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx); in addRegClassDefCounts()
1278 if (OpRC->hasSubClassEq(IdxRC)) in addRegClassDefCounts()
1285 for (unsigned RCIdx = 0, RCIdxEnd = TRI->getNumRegClasses(); in addRegClassDefCounts()
1287 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx); in addRegClassDefCounts()
1288 for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) { in addRegClassDefCounts()
1289 if (IdxRC->contains(*Alias)) { in addRegClassDefCounts()
1311 LLVM_DEBUG(dbgs() << "mark extra used: " << printReg(Reg, TRI) << '\n'); in findAndSortDefOperandIndexes()
1326 // used to assign registers for possibly-too-small classes first. Example: in findAndSortDefOperandIndexes()
1330 SmallVector<unsigned> RegClassDefCounts(TRI->getNumRegClasses(), 0); in findAndSortDefOperandIndexes()
1341 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in findAndSortDefOperandIndexes()
1342 const TargetRegisterClass &RC1 = *MRI->getRegClass(Reg1); in findAndSortDefOperandIndexes()
1366 // Tie-break rule: operand index. in findAndSortDefOperandIndexes()
1389 // - pre-assigned defs and uses need to be handled before the other def/use in allocateInstruction()
1391 // the pre-assignment. in allocateInstruction()
1392 // - The "free def operands" step has to come last instead of first for tied in allocateInstruction()
1393 // operands and early-clobbers. in allocateInstruction()
1404 // Scan for special cases; Apply pre-assigned register defs to state. in allocateInstruction()
1428 if (!MRI->isReserved(Reg)) { in allocateInstruction()
1450 // Note that Implicit MOs can get re-arranged by defineVirtReg(), so loop in allocateInstruction()
1456 // - Must not use a register that is pre-assigned for a use operand. in allocateInstruction()
1457 // - In order to solve tricky inline assembly constraints we change the in allocateInstruction()
1474 // Implicit operands of MI were re-arranged, in allocateInstruction()
1475 // re-compute DefOperandIndexes. in allocateInstruction()
1501 // defs first (we added them earlier in case of <def,read-undef>). in allocateInstruction()
1528 if (MRI->isReserved(Reg)) in allocateInstruction()
1540 MRI->addPhysRegsUsedFromRegMask(RM); in allocateInstruction()
1550 // Apply pre-assigned register uses to state. in allocateInstruction()
1558 if (MRI->isReserved(Reg)) in allocateInstruction()
1627 // early-clobber %x0 = INSTRUCTION %x0 in allocateInstruction()
1628 // which is semantically questionable as the early-clobber should in allocateInstruction()
1632 if (MI.readsRegister(Reg, TRI)) in allocateInstruction()
1662 if (SS != -1) { in handleDebugValue()
1676 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in handleDebugValue()
1679 setPhysReg(MI, *RegMO, LRI->PhysReg); in handleDebugValue()
1693 while (BundledMI->isBundledWithPred()) { in handleBundle()
1694 for (MachineOperand &MO : BundledMI->operands()) { in handleBundle()
1706 setPhysReg(MI, MO, DI->second); in handleBundle()
1714 this->MBB = &MBB; in allocateBasicBlock()
1718 RegUnitStates.assign(TRI->getNumRegUnits(), regFree); in allocateBasicBlock()
1760 assert(DbgValue->isDebugValue() && "expected DBG_VALUE"); in allocateBasicBlock()
1762 if (!DbgValue->hasDebugOperandForReg(UDBGPair.first)) in allocateBasicBlock()
1766 DbgValue->setDebugValueUndef(); in allocateBasicBlock()
1779 TRI = STI.getRegisterInfo(); in runOnMachineFunction()
1782 MRI->freezeReservedRegs(); in runOnMachineFunction()
1784 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction()
1788 // initialize the virtual->physical register map to have a 'null' in runOnMachineFunction()
1790 unsigned NumVirtRegs = MRI->getNumVirtRegs(); in runOnMachineFunction()
1803 MRI->clearVirtRegs(); in runOnMachineFunction()
1837 OS << "no-clear-vregs"; in printPipeline()