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Searched full:tx_clk (Results 1 – 17 of 17) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dcdns,macb.yaml87 - const: tx_clk
188 clock-names = "pclk", "hclk", "tx_clk";
216 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
H A Dmacb.txt28 Optional elements: 'tx_clk'
54 clock-names = "pclk", "hclk", "tx_clk";
H A Dqcom-emac.txt44 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
93 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
H A Dintel,dwmac-plat.yaml42 - const: tx_clk
110 clock-names = "stmmaceth", "ptp_ref", "tx_clk";
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dmicrochip,ksz.yaml70 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
76 Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc832x_rdb.dts180 3 23 2 0 1 0 /* TX_CLK (CLK3) */
200 3 24 2 0 1 0 /* TX_CLK (CLK10) */
H A Dmpc832x_mds.dts192 3 24 2 0 1 0 /* TX_CLK (CLK10) */
212 3 6 2 0 1 0 /* TX_CLK (CLK8) */
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10_socdk.dtsi75 * for TX_CLK on Arria 10.
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi253 clock-names = "pclk", "hclk", "tx_clk";
264 clock-names = "pclk", "hclk", "tx_clk";
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi744 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
758 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
772 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
786 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/freebsd/sys/dev/mii/
H A De1000phy.c290 /* Force TX_CLK to 25MHz clock. */ in e1000phy_reset()
/freebsd/sys/dev/cadence/
H A Dif_cgem.c1769 if (clk_get_by_ofw_name(dev, 0, "tx_clk", &sc->clk_txclk) == 0) { in cgem_attach()
1771 device_printf(dev, "could not enable tx_clk.\n"); in cgem_attach()
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dsama7g5.dtsi855 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
/freebsd/sys/dev/e1000/
H A De1000_phy.c1200 /* Force TX_CLK in the Extended PHY Specific Control Register in e1000_copper_link_setup_m88()
1815 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1927 /* Resetting the phy means we need to re-force TX_CLK in the in e1000_phy_force_speed_duplex_m88()
H A De1000_80003es2lan.c658 /* Resetting the phy means we need to verify the TX_CLK corresponds in e1000_phy_force_speed_duplex_80003es2lan()
H A De1000_defines.h1343 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
/freebsd/sys/dev/igc/
H A Digc_defines.h1163 #define M88IGC_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */