1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Principal Author: Parag Patel
5 * Copyright (c) 2001
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * Additional Copyright (c) 2001 by Traakan Software under same licence.
31 * Secondary Author: Matthew Jacob
32 */
33
34 #include <sys/cdefs.h>
35 /*
36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
37 */
38
39 /*
40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
41 * 1000baseSX PHY.
42 * Nathan Binkert <nate@openbsd.org>
43 * Jung-uk Kim <jkim@niksun.com>
44 */
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/socket.h>
51 #include <sys/bus.h>
52
53 #include <net/if.h>
54 #include <net/if_var.h>
55 #include <net/if_media.h>
56
57 #include <dev/mii/mii.h>
58 #include <dev/mii/miivar.h>
59 #include "miidevs.h"
60
61 #include <dev/mii/e1000phyreg.h>
62
63 #include "miibus_if.h"
64
65 static int e1000phy_probe(device_t);
66 static int e1000phy_attach(device_t);
67
68 static device_method_t e1000phy_methods[] = {
69 /* device interface */
70 DEVMETHOD(device_probe, e1000phy_probe),
71 DEVMETHOD(device_attach, e1000phy_attach),
72 DEVMETHOD(device_detach, mii_phy_detach),
73 DEVMETHOD(device_shutdown, bus_generic_shutdown),
74 DEVMETHOD_END
75 };
76
77 static driver_t e1000phy_driver = {
78 "e1000phy",
79 e1000phy_methods,
80 sizeof(struct mii_softc)
81 };
82
83 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, 0, 0);
84
85 static int e1000phy_service(struct mii_softc *, struct mii_data *, int);
86 static void e1000phy_status(struct mii_softc *);
87 static void e1000phy_reset(struct mii_softc *);
88 static int e1000phy_mii_phy_auto(struct mii_softc *, int);
89
90 static const struct mii_phydesc e1000phys[] = {
91 MII_PHY_DESC(MARVELL, E1000),
92 MII_PHY_DESC(MARVELL, E1011),
93 MII_PHY_DESC(MARVELL, E1000_3),
94 MII_PHY_DESC(MARVELL, E1000_5),
95 MII_PHY_DESC(MARVELL, E1111),
96 MII_PHY_DESC(xxMARVELL, E1000),
97 MII_PHY_DESC(xxMARVELL, E1011),
98 MII_PHY_DESC(xxMARVELL, E1000_3),
99 MII_PHY_DESC(xxMARVELL, E1000S),
100 MII_PHY_DESC(xxMARVELL, E1000_5),
101 MII_PHY_DESC(xxMARVELL, E1101),
102 MII_PHY_DESC(xxMARVELL, E3082),
103 MII_PHY_DESC(xxMARVELL, E1112),
104 MII_PHY_DESC(xxMARVELL, E1149),
105 MII_PHY_DESC(xxMARVELL, E1111),
106 MII_PHY_DESC(xxMARVELL, E1116),
107 MII_PHY_DESC(xxMARVELL, E1116R),
108 MII_PHY_DESC(xxMARVELL, E1116R_29),
109 MII_PHY_DESC(xxMARVELL, E1118),
110 MII_PHY_DESC(xxMARVELL, E1145),
111 MII_PHY_DESC(xxMARVELL, E1149R),
112 MII_PHY_DESC(xxMARVELL, E3016),
113 MII_PHY_DESC(xxMARVELL, PHYG65G),
114 MII_PHY_END
115 };
116
117 static const struct mii_phy_funcs e1000phy_funcs = {
118 e1000phy_service,
119 e1000phy_status,
120 e1000phy_reset
121 };
122
123 static int
e1000phy_probe(device_t dev)124 e1000phy_probe(device_t dev)
125 {
126
127 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT));
128 }
129
130 static int
e1000phy_attach(device_t dev)131 e1000phy_attach(device_t dev)
132 {
133 struct mii_softc *sc;
134
135 sc = device_get_softc(dev);
136
137 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0);
138
139 if (mii_dev_mac_match(dev, "msk") &&
140 (sc->mii_flags & MIIF_MACPRIV0) != 0)
141 sc->mii_flags |= MIIF_PHYPRIV0;
142
143 switch (sc->mii_mpd_model) {
144 case MII_MODEL_xxMARVELL_E1011:
145 case MII_MODEL_xxMARVELL_E1112:
146 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
147 sc->mii_flags |= MIIF_HAVEFIBER;
148 break;
149 case MII_MODEL_xxMARVELL_E1149:
150 case MII_MODEL_xxMARVELL_E1149R:
151 /*
152 * Some 88E1149 PHY's page select is initialized to
153 * point to other bank instead of copper/fiber bank
154 * which in turn resulted in wrong registers were
155 * accessed during PHY operation. It is believed that
156 * page 0 should be used for copper PHY so reinitialize
157 * E1000_EADR to select default copper PHY. If parent
158 * device know the type of PHY(either copper or fiber),
159 * that information should be used to select default
160 * type of PHY.
161 */
162 PHY_WRITE(sc, E1000_EADR, 0);
163 break;
164 }
165
166 PHY_RESET(sc);
167
168 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
169 if (sc->mii_capabilities & BMSR_EXTSTAT) {
170 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
171 if ((sc->mii_extcapabilities &
172 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
173 sc->mii_flags |= MIIF_HAVE_GTCR;
174 }
175 device_printf(dev, " ");
176 mii_phy_add_media(sc);
177 printf("\n");
178
179 MIIBUS_MEDIAINIT(sc->mii_dev);
180 return (0);
181 }
182
183 static void
e1000phy_reset(struct mii_softc * sc)184 e1000phy_reset(struct mii_softc *sc)
185 {
186 uint16_t reg, page;
187
188 reg = PHY_READ(sc, E1000_SCR);
189 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
190 reg &= ~E1000_SCR_AUTO_X_MODE;
191 PHY_WRITE(sc, E1000_SCR, reg);
192 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) {
193 /* Select 1000BASE-X only mode. */
194 page = PHY_READ(sc, E1000_EADR);
195 PHY_WRITE(sc, E1000_EADR, 2);
196 reg = PHY_READ(sc, E1000_SCR);
197 reg &= ~E1000_SCR_MODE_MASK;
198 reg |= E1000_SCR_MODE_1000BX;
199 PHY_WRITE(sc, E1000_SCR, reg);
200 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) {
201 /* Set SIGDET polarity low for SFP module. */
202 PHY_WRITE(sc, E1000_EADR, 1);
203 reg = PHY_READ(sc, E1000_SCR);
204 reg |= E1000_SCR_FIB_SIGDET_POLARITY;
205 PHY_WRITE(sc, E1000_SCR, reg);
206 }
207 PHY_WRITE(sc, E1000_EADR, page);
208 }
209 } else {
210 switch (sc->mii_mpd_model) {
211 case MII_MODEL_xxMARVELL_E1111:
212 case MII_MODEL_xxMARVELL_E1112:
213 case MII_MODEL_xxMARVELL_E1116:
214 case MII_MODEL_xxMARVELL_E1116R_29:
215 case MII_MODEL_xxMARVELL_E1118:
216 case MII_MODEL_xxMARVELL_E1149:
217 case MII_MODEL_xxMARVELL_E1149R:
218 case MII_MODEL_xxMARVELL_PHYG65G:
219 /* Disable energy detect mode. */
220 reg &= ~E1000_SCR_EN_DETECT_MASK;
221 reg |= E1000_SCR_AUTO_X_MODE;
222 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
223 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29)
224 reg &= ~E1000_SCR_POWER_DOWN;
225 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
226 break;
227 case MII_MODEL_xxMARVELL_E3082:
228 reg |= (E1000_SCR_AUTO_X_MODE >> 1);
229 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
230 break;
231 case MII_MODEL_xxMARVELL_E3016:
232 reg |= E1000_SCR_AUTO_MDIX;
233 reg &= ~(E1000_SCR_EN_DETECT |
234 E1000_SCR_SCRAMBLER_DISABLE);
235 reg |= E1000_SCR_LPNP;
236 /* XXX Enable class A driver for Yukon FE+ A0. */
237 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
238 break;
239 default:
240 reg &= ~E1000_SCR_AUTO_X_MODE;
241 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
242 break;
243 }
244 if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) {
245 /* Auto correction for reversed cable polarity. */
246 reg &= ~E1000_SCR_POLARITY_REVERSAL;
247 }
248 PHY_WRITE(sc, E1000_SCR, reg);
249
250 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
251 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29 ||
252 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 ||
253 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) {
254 PHY_WRITE(sc, E1000_EADR, 2);
255 reg = PHY_READ(sc, E1000_SCR);
256 reg |= E1000_SCR_RGMII_POWER_UP;
257 PHY_WRITE(sc, E1000_SCR, reg);
258 PHY_WRITE(sc, E1000_EADR, 0);
259 }
260 }
261
262 switch (sc->mii_mpd_model) {
263 case MII_MODEL_xxMARVELL_E3082:
264 case MII_MODEL_xxMARVELL_E1112:
265 case MII_MODEL_xxMARVELL_E1118:
266 break;
267 case MII_MODEL_xxMARVELL_E1116:
268 case MII_MODEL_xxMARVELL_E1116R_29:
269 page = PHY_READ(sc, E1000_EADR);
270 /* Select page 3, LED control register. */
271 PHY_WRITE(sc, E1000_EADR, 3);
272 PHY_WRITE(sc, E1000_SCR,
273 E1000_SCR_LED_LOS(1) | /* Link/Act */
274 E1000_SCR_LED_INIT(8) | /* 10Mbps */
275 E1000_SCR_LED_STAT1(7) | /* 100Mbps */
276 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */
277 /* Set blink rate. */
278 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
279 E1000_BLINK_RATE(E1000_BLINK_84MS));
280 PHY_WRITE(sc, E1000_EADR, page);
281 break;
282 case MII_MODEL_xxMARVELL_E3016:
283 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
284 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
285 /* Integrated register calibration workaround. */
286 PHY_WRITE(sc, 0x1D, 17);
287 PHY_WRITE(sc, 0x1E, 0x3F60);
288 break;
289 default:
290 /* Force TX_CLK to 25MHz clock. */
291 reg = PHY_READ(sc, E1000_ESCR);
292 reg |= E1000_ESCR_TX_CLK_25;
293 PHY_WRITE(sc, E1000_ESCR, reg);
294 break;
295 }
296
297 /* Reset the PHY so all changes take effect. */
298 reg = PHY_READ(sc, E1000_CR);
299 reg |= E1000_CR_RESET;
300 PHY_WRITE(sc, E1000_CR, reg);
301 }
302
303 static int
e1000phy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)304 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
305 {
306 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
307 uint16_t speed, gig;
308 int reg;
309
310 switch (cmd) {
311 case MII_POLLSTAT:
312 break;
313
314 case MII_MEDIACHG:
315 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
316 e1000phy_mii_phy_auto(sc, ife->ifm_media);
317 break;
318 }
319
320 speed = 0;
321 switch (IFM_SUBTYPE(ife->ifm_media)) {
322 case IFM_1000_T:
323 if ((sc->mii_flags & MIIF_HAVE_GTCR) == 0)
324 return (EINVAL);
325 speed = E1000_CR_SPEED_1000;
326 break;
327 case IFM_1000_SX:
328 if ((sc->mii_extcapabilities &
329 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
330 return (EINVAL);
331 speed = E1000_CR_SPEED_1000;
332 break;
333 case IFM_100_TX:
334 speed = E1000_CR_SPEED_100;
335 break;
336 case IFM_10_T:
337 speed = E1000_CR_SPEED_10;
338 break;
339 case IFM_NONE:
340 reg = PHY_READ(sc, E1000_CR);
341 PHY_WRITE(sc, E1000_CR,
342 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
343 goto done;
344 default:
345 return (EINVAL);
346 }
347
348 if ((ife->ifm_media & IFM_FDX) != 0) {
349 speed |= E1000_CR_FULL_DUPLEX;
350 gig = E1000_1GCR_1000T_FD;
351 } else
352 gig = E1000_1GCR_1000T;
353
354 reg = PHY_READ(sc, E1000_CR);
355 reg &= ~E1000_CR_AUTO_NEG_ENABLE;
356 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
357
358 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
359 gig |= E1000_1GCR_MS_ENABLE;
360 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
361 gig |= E1000_1GCR_MS_VALUE;
362 } else if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0)
363 gig = 0;
364 PHY_WRITE(sc, E1000_1GCR, gig);
365 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
366 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
367 done:
368 break;
369 case MII_TICK:
370 /*
371 * Only used for autonegotiation.
372 */
373 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
374 sc->mii_ticks = 0;
375 break;
376 }
377
378 /*
379 * check for link.
380 * Read the status register twice; BMSR_LINK is latch-low.
381 */
382 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
383 if (reg & BMSR_LINK) {
384 sc->mii_ticks = 0;
385 break;
386 }
387
388 /* Announce link loss right after it happens. */
389 if (sc->mii_ticks++ == 0)
390 break;
391 if (sc->mii_ticks <= sc->mii_anegticks)
392 break;
393
394 sc->mii_ticks = 0;
395 PHY_RESET(sc);
396 e1000phy_mii_phy_auto(sc, ife->ifm_media);
397 break;
398 }
399
400 /* Update the media status. */
401 PHY_STATUS(sc);
402
403 /* Callback if something changed. */
404 mii_phy_update(sc, cmd);
405 return (0);
406 }
407
408 static void
e1000phy_status(struct mii_softc * sc)409 e1000phy_status(struct mii_softc *sc)
410 {
411 struct mii_data *mii = sc->mii_pdata;
412 int bmcr, bmsr, ssr;
413
414 mii->mii_media_status = IFM_AVALID;
415 mii->mii_media_active = IFM_ETHER;
416
417 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
418 bmcr = PHY_READ(sc, E1000_CR);
419 ssr = PHY_READ(sc, E1000_SSR);
420
421 if (bmsr & E1000_SR_LINK_STATUS)
422 mii->mii_media_status |= IFM_ACTIVE;
423
424 if (bmcr & E1000_CR_LOOPBACK)
425 mii->mii_media_active |= IFM_LOOP;
426
427 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
428 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
429 /* Erg, still trying, I guess... */
430 mii->mii_media_active |= IFM_NONE;
431 return;
432 }
433
434 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
435 switch (ssr & E1000_SSR_SPEED) {
436 case E1000_SSR_1000MBS:
437 mii->mii_media_active |= IFM_1000_T;
438 break;
439 case E1000_SSR_100MBS:
440 mii->mii_media_active |= IFM_100_TX;
441 break;
442 case E1000_SSR_10MBS:
443 mii->mii_media_active |= IFM_10_T;
444 break;
445 default:
446 mii->mii_media_active |= IFM_NONE;
447 return;
448 }
449 } else {
450 /*
451 * Some fiber PHY(88E1112) does not seem to set resolved
452 * speed so always assume we've got IFM_1000_SX.
453 */
454 mii->mii_media_active |= IFM_1000_SX;
455 }
456
457 if (ssr & E1000_SSR_DUPLEX) {
458 mii->mii_media_active |= IFM_FDX;
459 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0)
460 mii->mii_media_active |= mii_phy_flowstatus(sc);
461 } else
462 mii->mii_media_active |= IFM_HDX;
463
464 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
465 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) &
466 E1000_1GSR_MS_CONFIG_RES) != 0)
467 mii->mii_media_active |= IFM_ETH_MASTER;
468 }
469 }
470
471 static int
e1000phy_mii_phy_auto(struct mii_softc * sc,int media)472 e1000phy_mii_phy_auto(struct mii_softc *sc, int media)
473 {
474 uint16_t reg;
475
476 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
477 reg = PHY_READ(sc, E1000_AR);
478 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR);
479 reg |= E1000_AR_10T | E1000_AR_10T_FD |
480 E1000_AR_100TX | E1000_AR_100TX_FD;
481 if ((media & IFM_FLOW) != 0 ||
482 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
483 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR;
484 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
485 } else
486 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X);
487 if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
488 reg = 0;
489 if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0)
490 reg |= E1000_1GCR_1000T_FD;
491 if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0)
492 reg |= E1000_1GCR_1000T;
493 PHY_WRITE(sc, E1000_1GCR, reg);
494 }
495 PHY_WRITE(sc, E1000_CR,
496 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
497
498 return (EJUSTRETURN);
499 }
500