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/linux/arch/arm/crypto/
H A Daes-ce-core.S51 enc_round q2, \key1
55 enc_round q2, \key2
62 dec_round q2, \key1
66 dec_round q2, \key2
73 enc_round q2, \key1
77 aese.8 q2, \key2
81 veor q2, q2, \key3
88 dec_round q2, \key1
92 aesd.8 q2, \key2
96 veor q2, q2, \key3
[all …]
H A Dchacha-neon-core.S79 vadd.i32 q2, q2, q3
80 veor q4, q1, q2
91 vadd.i32 q2, q2, q3
92 veor q4, q1, q2
99 vext.8 q2, q2, q2, #8
109 vadd.i32 q2, q2, q3
110 veor q4, q1, q2
121 vadd.i32 q2, q2, q3
122 veor q4, q1, q2
129 vext.8 q2, q2, q2, #8
[all …]
H A Dcurve25519-core.S35 vmov.i32 q2, #0
58 vmov.i64 q2, #0xffffffff
59 vshr.u64 q3, q2, #7
60 vshr.u64 q2, q2, #6
84 vand q4, q4, q2
85 vand q6, q6, q2
86 vand q8, q8, q2
87 vand q10, q10, q2
88 vand q2, q12, q2
112 vadd.i64 q2, q2, q13
[all …]
H A Dcrc32-ce-core.S136 vld1.8 {q1-q2}, [BUF, :128]!
157 vmull.p64 q2, d4, dCONSTANTl
163 veor.8 q2, q2, q6
171 veor.8 q2, q2, q6
185 veor.8 q1, q1, q2
203 vld1.8 {q2}, [BUF, :128]!
207 veor.8 q1, q1, q2
214 vmull.p64 q2, d2, dCONSTANTh
216 veor.8 q1, q1, q2
223 vext.8 q2, q1, qzr, #4
[all …]
H A Daes-neonbs-core.S456 vtst.8 q2, q7, q10
470 vst1.8 {q2-q3}, [r0, :256]!
491 veor q12, q2, q9
494 __tbl q2, q12, q8
505 bitslice q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11
517 shift_rows q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12
519 sbox q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, \
524 mix_cols q0, q1, q4, q6, q3, q7, q2, q5, q8, q9, q10, q11, q12, \
534 bitslice q0, q1, q4, q6, q3, q7, q2, q5, q8, q9, q10, q11
542 veor q2, q2, q12
[all …]
H A Dblake2b-neon-core.S77 vadd.u64 q0, q0, q2
96 veor q2, q2, q4
111 vadd.u64 q0, q0, q2
136 veor q8, q2, q4
138 vshr.u64 q2, q8, #63
140 vsli.u64 q2, q8, #1
226 vshr.u64 q2, q8, #63
228 vsli.u64 q2, q8, #1
260 vld1.64 {q2-q3}, [ip]! // Load h[4..7]
318 veor q2, q2, q6 // v[4..5] ^= v[12..13]
[all …]
H A Dcrct10dif-ce-core.S168 vld1.64 {q2-q3}, [buf]!
173 CPU_LE( vrev64.8 q2, q2 )
204 fold_32_bytes q2, q3
216 fold_16_bytes q2, q6
267 vld1.8 {q2}, [r3]
273 veor.8 q2, q2, q3
278 vshr.s8 q2, q2, #7
280 // q2 = second chunk: 'len' bytes from q0 (low-order bytes),
282 vbsl.8 q2, q1, q0
288 veor.8 q7, q7, q2
H A Dsha2-ce-core.S79 vld1.32 {q2-q3}, [r1]!
85 vrev32.8 q2, q2
H A Dnh-neon-core.S26 PASS2_SUMS .req q2
/linux/tools/testing/selftests/sgx/
H A Dsigstruct.c32 BIGNUM *q2;
42 BN_free(ctx->q2); in free_q1q2_ctx()
53 ctx->q2 = BN_new(); in alloc_q1q2_ctx()
56 !ctx->q2) { in alloc_q1q2_ctx()
81 uint8_t *q2) in calc_q1q2()
103 if (!BN_mul(ctx.q2, ctx.s, ctx.qr, ctx.bn_ctx)) in calc_q1q2()
106 if (!BN_div(ctx.q2, NULL, ctx.q2, ctx.m, ctx.bn_ctx)) in calc_q1q2()
109 if (BN_num_bytes(ctx.q2) > SGX_MODULUS_SIZE) { in calc_q1q2()
110 fprintf(stderr, "Too large Q2 in calc_q1q2()
31 BIGNUM *q2; global() member
80 calc_q1q2(const uint8_t * s,const uint8_t * m,uint8_t * q1,uint8_t * q2) calc_q1q2() argument
[all...]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h633 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
636 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2)
646 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
647 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
649 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
650 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
652 uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC
659 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
660 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
661 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
[all …]
H A Dsmu11_driver_if_arcturus.h497 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
504 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
505 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
506 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
507 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
526 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
583 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
588 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2
589 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2
591 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2
[all …]
H A Dsmu11_driver_if_navi10.h558 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
559 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
569 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
570 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
574 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
575 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
576 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
577 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
603 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
604 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
[all …]
H A Dsmu13_driver_if_v13_0_0.h863 uint16_t InitGfx; // In mV(Q2) , should be 0?
864 uint16_t InitSoc; // In mV(Q2)
865 uint16_t InitU; // In Mv(Q2)
919 uint16_t DcTol; // mV Q2
920 uint16_t DcBtcGb; // mV Q2
922 uint16_t DcBtcMin; // mV Q2
923 uint16_t DcBtcMax; // mV Q2
932 uint16_t VInversion; // in mV Q2
995 …uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV…
997 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE)
[all …]
H A Dsmu13_driver_if_v13_0_7.h872 uint16_t InitGfx; // In mV(Q2) , should be 0?
873 uint16_t InitSoc; // In mV(Q2)
874 uint16_t InitU; // In Mv(Q2) not applicable
928 uint16_t DcTol; // mV Q2
929 uint16_t DcBtcGb; // mV Q2
931 uint16_t DcBtcMin; // mV Q2
932 uint16_t DcBtcMax; // mV Q2
941 uint16_t VInversion; // in mV Q2
1004 …uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV…
1006 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE)
[all …]
H A Dsmu14_driver_if_v14_0.h964 uint16_t InitGfx; // In mV(Q2) , should be 0?
965 uint16_t InitSoc; // In mV(Q2)
966 uint16_t InitVddIoMem; // In mV(Q2) MemVdd
967 uint16_t InitVddCiMem; // In mV(Q2) VMemP
1019 uint16_t DcTol; // mV Q2
1020 uint16_t DcBtcGb; // mV Q2
1022 uint16_t DcBtcMin; // mV Q2
1023 uint16_t DcBtcMax; // mV Q2
1031 uint16_t VInversion; // in mV Q2
1094 …uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV…
[all …]
/linux/arch/arm/include/asm/
H A Ddiv64.h61 asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" in __arch_xprod_64()
68 asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" in __arch_xprod_64()
74 asm ( "umull %Q0, %R0, %Q2, %Q3\n\t" in __arch_xprod_64()
75 "cmn %Q0, %Q2\n\t" in __arch_xprod_64()
84 asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" in __arch_xprod_64()
93 "umlal %R0, %1, %Q2, %R3\n\t" in __arch_xprod_64()
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-srggb8-pisp-comp.rst48 (q1,q2) both in the range [384..511], they are coded using 9 bits for q1
49 followed by 7 bits for (q2 & 127). Otherwise, for quantization modes
50 0, 1 and 2: a 9-bit field encodes MIN(q1,q2) which must be in the range
51 [0..511] and a 7-bit field encodes (q2-q1+64) which must be in [0..127].
54 on its inner neighbour q1 or q2. In quantization mode 2 where the inner
57 is encoded as (q0-MAX(0,q1-64)). q3 is likewise coded based on q2.
68 Each pair of quantized pixels (q0,q1) or (q2,q3) is jointly coded
/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h176 #define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */
177 #define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */
178 #define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */
179 #define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */
180 #define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */
181 #define B4_R2_F 0x0260 /* 32 bit flag register (q2) */
182 #define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */
183 #define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */
184 #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */
185 #define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */
[all …]
/linux/arch/m68k/fpsp040/
H A Dstan.S34 | V = 1 + s*(Q1 + s*(Q2 + s*(Q3 + s*Q4))), s = r*r.
40 | V = 1 + s*(Q1 + s*(Q2 + s*(Q3 + s*Q4))), s = r*r,
229 faddx TANQ2,%fp3 | ...Q2+S(Q3+SQ4)
232 fmulx %fp1,%fp3 | ...S(Q2+S(Q3+SQ4))
235 faddx TANQ1,%fp3 | ...Q1+S(Q2+S(Q3+SQ4))
238 fmulx %fp3,%fp1 | ...S(Q1+S(Q2+S(Q3+SQ4)))
267 faddx TANQ2,%fp3 | ...Q2+S(Q3+SQ4)
270 fmulx %fp0,%fp3 | ...S(Q2+S(Q3+SQ4))
273 faddx TANQ1,%fp3 | ...Q1+S(Q2+S(Q3+SQ4))
276 fmulx %fp3,%fp0 | ...S(Q1+S(Q2+S(Q3+SQ4)))
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm4709-netgear-r8000.dts143 brcm,ccode-map = "JP-JP-78", "US-Q2-86";
173 brcm,ccode-map = "JP-JP-78", "US-Q2-86";
187 brcm,ccode-map = "JP-JP-78", "US-Q2-86";
H A Dbcm47094-luxul-xwr-3150-v1.dts97 brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
115 brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-latch.yaml21 OUT2 ------------+-|-|--|-----------|D2 Q2|-----|<
34 | | | | | `------------------|D2 Q2|-----|<
/linux/include/sound/sof/
H A Dchannel_map.h33 * Channel mask is followed by array of coefficients in Q2.30 format,
/linux/tools/testing/selftests/arm64/fp/
H A Dfp-ptrace-asm.S30 ldp q2, q3, [x7, #16 * 2]
152 stp q2, q3, [x7, #16 * 2]

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