Lines Matching full:q2
176 #define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */
177 #define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */
178 #define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */
179 #define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */
180 #define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */
181 #define B4_R2_F 0x0260 /* 32 bit flag register (q2) */
182 #define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */
183 #define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */
184 #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */
185 #define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */
186 #define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */
187 #define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */
188 #define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */
321 #define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
322 #define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
323 #define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
324 #define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
370 #define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
371 #define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
372 #define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
373 #define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
516 /* B4_R2_D 4*32 bit current receive Descriptor (q2) */
517 /* B4_R2_DA 32 bit current rec desc address (q2) */
518 /* B4_R2_AC 32 bit current receive Address Count (q2) */
519 /* B4_R2_BC 32 bit current receive Byte Counter (q2) */
520 /* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */
521 /* B4_R2_F 32 bit flag register (q2) */
522 /* B4_R2_T1 32 bit Test Register 1 (q2) */
523 /* B4_R2_T2 32 bit Test Register 2 (q2) */
524 /* B4_R2_T3 32 bit Test Register 3 (q2) */