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/linux/drivers/clk/samsung/
H A Dclk-exynos2200.c736 PNAME(mout_cmu_cp_mpll_clk_d2_user_parents) = { "oscclk" };
737 PNAME(mout_cmu_cp_mpll_clk_user_parents) = { "oscclk" };
743 "oscclk", "oscclk",
744 "oscclk" };
750 "oscclk", "oscclk",
751 "oscclk" };
770 "oscclk", "oscclk" };
777 "oscclk", "oscclk" };
784 "oscclk", "oscclk" };
792 "oscclk" };
[all …]
H A Dclk-exynos8895.c501 PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
504 PLL(pll_1051x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
507 PLL(pll_1052x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
510 PLL(pll_1052x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
513 PLL(pll_1052x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
519 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
520 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
521 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
522 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
523 PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
[all …]
H A Dclk-exynos990.c453 PLL(pll_0717x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
455 PLL(pll_0717x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
457 PLL(pll_0718x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
459 PLL(pll_0718x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
461 PLL(pll_0717x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
463 PLL(pll_0732x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
465 PLL(pll_0718x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
470 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
471 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
472 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
[all …]
H A Dclk-exynosautov920.c335 PLL(pll_531x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
337 PLL(pll_531x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
339 PLL(pll_531x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
341 PLL(pll_531x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
343 PLL(pll_531x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
345 PLL(pll_531x, FOUT_SHARED5_PLL, "fout_shared5_pll", "oscclk",
347 PLL(pll_531x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
352 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
353 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
354 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
[all …]
H A Dclk-exynos7885.c156 PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
159 PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
165 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
166 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
178 PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" };
179 PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" };
180 PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" };
181 PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" };
182 PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" };
183 PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
[all …]
H A Dclk-gs101.c642 PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
645 PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
648 PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
651 PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
654 PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
660 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
661 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
662 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
663 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
664 PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" };
[all …]
H A Dclk-exynos850.c233 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
236 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
239 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
244 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
245 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
246 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
257 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
260 "oscclk", "oscclk" };
276 PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
279 "oscclk", "oscclk" };
[all …]
H A Dclk-exynos7870.c297 PLL(pll_1417x, CLK_FOUT_MIF_BUS_PLL, "fout_mif_bus_pll", "oscclk",
299 PLL(pll_1417x, CLK_FOUT_MIF_MEDIA_PLL, "fout_mif_media_pll", "oscclk",
301 PLL(pll_1417x, CLK_FOUT_MIF_MEM_PLL, "fout_mif_mem_pll", "oscclk",
327 "oscclk" };
329 "oscclk" };
331 "oscclk" };
344 "oscclk" };
346 "oscclk" };
348 "oscclk" };
350 "oscclk" };
[all …]
H A Dclk-exynosautov9.c353 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
355 PLL(pll_0822x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
357 PLL(pll_0822x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
359 PLL(pll_0822x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
361 PLL(pll_0822x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
366 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
367 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
368 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
369 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
370 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
[all …]
H A Dclk-exynos5433.c210 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
211 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
212 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
213 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
214 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
215 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
216 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
217 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
248 "oscclk", "ioclk_spdif_extclk", };
249 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
[all …]
H A Dclk-cpu.c413 /* OSCCLK clock rate, Hz */
490 /* No actions are needed when switching to or from OSCCLK parent */ in exynos850_cpuclk_pre_rate_change()
550 /* No actions are needed when switching to or from OSCCLK parent */ in exynos850_cpuclk_post_rate_change()
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos8895-clock.yaml18 is an external clock: OSCCLK (26 MHz). This external clock must be defined
81 - const: oscclk
106 - const: oscclk
132 - const: oscclk
169 - const: oscclk
201 - const: oscclk
218 - const: oscclk
231 clocks = <&oscclk>,
236 clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
H A Dsamsung,exynos990-clock.yaml18 is an external clock: OSCCLK (26 MHz). This external clock must be defined
79 - const: oscclk
101 - const: oscclk
122 - const: oscclk
139 - const: oscclk
152 clocks = <&oscclk>,
157 clock-names = "oscclk",
H A Dsamsung,exynos7885-clock.yaml20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
68 - const: oscclk
87 - const: oscclk
111 - const: oscclk
141 - const: oscclk
171 clocks = <&oscclk>,
181 clock-names = "oscclk",
H A Dsamsung,exynos-ext-clock.yaml23 - samsung,exynos5420-oscclk
H A Daxis,artpec8-clock.yaml16 The root clock in that root tree is an external clock: OSCCLK (25 MHz).
/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos-hdmi.yaml121 - description: MUX used to switch between oscclk and tmds_clko,
124 - description: MUX used to switch between oscclk and pixel_clko,
139 - const: oscclk
195 "oscclk",
/linux/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2600-pinctrl.yaml143 - OSCCLK
372 - OSCCLK
H A Daspeed,ast2700-soc1-pinctrl.yaml159 - OSCCLK
397 - OSCCLK
H A Daspeed,ast2400-pinctrl.yaml116 - OSCCLK
H A Daspeed,ast2500-pinctrl.yaml135 - OSCCLK
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420-smdk5420.dts35 oscclk {
36 compatible = "samsung,exynos5420-oscclk";
H A Dexynos5422-samsung-k3g.dts32 oscclk {
33 compatible = "samsung,exynos5420-oscclk";
H A Dexynos5420-galaxy-tab-common.dtsi52 oscclk {
53 compatible = "samsung,exynos5420-oscclk";
H A Dexynos5420-arndale-octa.dts41 oscclk {
42 compatible = "samsung,exynos5420-oscclk";

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