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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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/freebsd/share/man/man4/
H A Dre.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
59 NICs based on the 8139C+ and 810xE are capable of 10 and 100Mbps speeds
61 NICs based on the 8169, 816xS, 811xS, 8168 and 8111 are capable of 10, 100
67 features, and use a descriptor-based DMA mechanism.
69 capable of TCP large send (TCP segmentation offload).
71 The 8139C+ is a single-chip solution combining both a 10/100 MAC and PHY.
73 The 816xS, 811xS, 8168 and 8111 are single-chip devices containing both a
76 in both 32-bit PCI and 64-bit PCI models.
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H A Dahci.41 .\" Copyright (c) 2009-2013 Alexander Motin <mav@FreeBSD.org>
35 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
50 .Bl -ohang
51 .It Va hint.ahci. Ns Ar X Ns Va .msi
52 controls Message Signaled Interrupts (MSI) usage by the specified controller.
54 .Bl -tag -width 4n -offset indent -compact
58 single MSI vector used, if supported;
60 multiple MSI vectors used, if supported (default);
64 Non-zero value enables CCC and defines maximum time (in ms), request can wait
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H A Dmxge.442 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
87 .Bl -bullet -compact
89 Myricom 10GBase-CX4 (10G-PCIE-8A-C, 10G-PCIE-8AL-C)
91 Myricom 10GBase-R (10G-PCIE-8A-R, 10G-PCIE-8AL-R)
93 Myricom 10G XAUI over ribbon fiber (10G-PCIE-8A-Q, 10G-PCIE-8AL-Q)
100 .Bl -tag -width indent
112 A non-zero value
117 using MSI or MSI-X interrupts.
128 both be capable of MSI-X.
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H A Dbge.416 .\" 4. Neither the name of the author nor the names of any co-contributors
42 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
60 All of these NICs are capable of 10, 100 and 1000Mbps speeds over CAT5
61 copper cable, except for the SysKonnect SK-9D41 which supports only
64 It has two R4000 CPU cores and is PCI v2.2 and PCI-X v1.0 compliant.
67 multiple RX and TX DMA rings for QoS applications, rules-based
69 a 256-bit multicast hash filter.
71 provided via value-add firmware updates.
78 Most BCM5700-based cards also use the Broadcom BCM5401 or BCM5411 10/100/1000
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H A Dnvme.42 .\" Copyright (c) 2012-2016 Intel Corporation
43 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
65 .Bl -bullet
69 Per-CPU IO queue pairs
93 will create an I/O queue pair for each CPU, provided enough MSI-X vectors
102 .Bd -literal -offset indent
107 of MSI-X vectors consumed by the device, set the following tunable value in
109 .Bd -literal -offset indent
117 .Bd -literal -offset indent
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
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H A Dplda,xpressrich3-axi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
11 - Kevin Xie <kevin.xie@starfivetech.com>
17 - $ref: /schemas/pci/pci-host-bridge.yaml#
23 reg-names:
25 - const: cfg
26 - const: apb
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H A Dbaikal,bt1-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
15 to have just a single Root Port function and is capable of establishing the
18 performed by software. There four in- and four outbound iATU regions
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H A Dxlnx,nwl-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pci
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H A Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dmarvell,xor-v2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
15 - const: marvell,xor-v2
16 - items:
17 - enum:
18 - marvell,armada-7k-xor
19 - const: marvell,xor-v2
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H A Dmv-xor-v2.txt4 - compatible: one of the following values:
5 "marvell,armada-7k-xor"
6 "marvell,xor-v2"
7 - reg: Should contain registers location and length (two sets)
10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
14 - clocks: Optional reference to the clocks used by the XOR engine.
15 - clock-names: mandatory if there is a second clock, in this case the
23 compatible = "marvell,xor-v2";
26 msi-parent = <&gic_v2m0>;
27 dma-coherent;
H A Dqcom_hidma_mgmt.txt18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
41 Sub-nodes:
50 - compatible: must contain "qcom,hidma-1.0" for initial HW or
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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/freebsd/sys/dev/cxgbe/firmware/
H A Dt5fw_cfg_fpga.txt3 # Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
31 # And finally, all Physical Funcations capable of supporting Virtual
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
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H A Dt4fw_cfg_uwire.txt3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
31 # And finally, all Physical Funcations capable of supporting Virtual
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
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/freebsd/sys/amd64/vmm/io/
H A Dppt.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 * If the MSI-X table is located in the middle of a BAR then that MMIO
60 * region gets split into two segments - one segment above the MSI-X table
61 * and the other segment below the MSI-X table - with a hole in place of
62 * the MSI-X table so accesses to it can be trapped and emulated.
68 MALLOC_DEFINE(M_PPTMSIX, "pptmsix", "Passthru MSI-X resources");
94 } msi; member
133 * - be allowed by administrator to be used in this role in ppt_probe()
134 * - be an endpoint device in ppt_probe()
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/freebsd/sys/dev/vmd/
H A Dvmd.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
81 * By default all VMD devices remap children MSI/MSI-X interrupts into their
87 "Bypass MSI remapping on capable hardware");
96 "Maximum number of MSI vectors per device");
99 * MSI-X can use different addresses, but we have limited number of MSI-X
104 "Maximum number of MSI-X vectors per device");
126 for (t = vmd_devs; t->vmd_name != NULL; t++) { in vmd_probe()
127 if (vid == t->vmd_vid && did == t->vmd_did) { in vmd_probe()
128 device_set_desc(dev, t->vmd_name); in vmd_probe()
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/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2838_pci.c1 /*-
2 * SPDX-License-Identifier: ISC
22 * BCM2838-compatible PCI-express controller.
95 * is 8 GiB). However, the system DMA controller is capable of accessing only a
96 * limited portion of the address space. Worse, the PCI-e controller has further
108 #define REG_VALUE_DMA_WINDOW_LOW (MAX_MEMORY_LOG2 - 0xf)
112 (((MAX_MEMORY_LOG2 - 0xf) << 0x1b) | DMA_WINDOW_ENABLE)
135 {"brcm,bcm2711-pcie", 1},
136 {"brcm,bcm7211-pcie", 1},
137 {"brcm,bcm7445-pcie", 1},
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/freebsd/sys/contrib/xen/
H A Dphysdev.h32 * @args == Operation-specific extra arguments (NULL if none).
36 * Notify end-of-interrupt (EOI) for the specified IRQ.
105 * Set the current VCPU's I/O-port permissions bitmap.
122 * Read or write an IO-APIC register.
167 /* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
312 * MSI-X capable devices won't (prepare) or may (release) change.
344 * Notify that some PIRQ-bound event channels have been unmasked.
352 * These all-capitals physdev operation names are superceded by the new names
354 * added post-4.5 only though and hence shouldn't check for 0x00030202.
378 * c-file-style: "BSD"
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/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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