xref: /freebsd/sys/contrib/xen/physdev.h (revision 3a9fd8242b35884921dfc4e886f284a75870a536)
1*3a9fd824SRoger Pau Monné /*
2*3a9fd824SRoger Pau Monné  * Permission is hereby granted, free of charge, to any person obtaining a copy
3*3a9fd824SRoger Pau Monné  * of this software and associated documentation files (the "Software"), to
4*3a9fd824SRoger Pau Monné  * deal in the Software without restriction, including without limitation the
5*3a9fd824SRoger Pau Monné  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
6*3a9fd824SRoger Pau Monné  * sell copies of the Software, and to permit persons to whom the Software is
7*3a9fd824SRoger Pau Monné  * furnished to do so, subject to the following conditions:
8*3a9fd824SRoger Pau Monné  *
9*3a9fd824SRoger Pau Monné  * The above copyright notice and this permission notice shall be included in
10*3a9fd824SRoger Pau Monné  * all copies or substantial portions of the Software.
11*3a9fd824SRoger Pau Monné  *
12*3a9fd824SRoger Pau Monné  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13*3a9fd824SRoger Pau Monné  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14*3a9fd824SRoger Pau Monné  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
15*3a9fd824SRoger Pau Monné  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
16*3a9fd824SRoger Pau Monné  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
17*3a9fd824SRoger Pau Monné  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
18*3a9fd824SRoger Pau Monné  * DEALINGS IN THE SOFTWARE.
19*3a9fd824SRoger Pau Monné  *
20*3a9fd824SRoger Pau Monné  * Copyright (c) 2006, Keir Fraser
21*3a9fd824SRoger Pau Monné  */
22*3a9fd824SRoger Pau Monné 
23*3a9fd824SRoger Pau Monné #ifndef __XEN_PUBLIC_PHYSDEV_H__
24*3a9fd824SRoger Pau Monné #define __XEN_PUBLIC_PHYSDEV_H__
25*3a9fd824SRoger Pau Monné 
26*3a9fd824SRoger Pau Monné #include "xen.h"
27*3a9fd824SRoger Pau Monné 
28*3a9fd824SRoger Pau Monné /*
29*3a9fd824SRoger Pau Monné  * Prototype for this hypercall is:
30*3a9fd824SRoger Pau Monné  *  int physdev_op(int cmd, void *args)
31*3a9fd824SRoger Pau Monné  * @cmd  == PHYSDEVOP_??? (physdev operation).
32*3a9fd824SRoger Pau Monné  * @args == Operation-specific extra arguments (NULL if none).
33*3a9fd824SRoger Pau Monné  */
34*3a9fd824SRoger Pau Monné 
35*3a9fd824SRoger Pau Monné /*
36*3a9fd824SRoger Pau Monné  * Notify end-of-interrupt (EOI) for the specified IRQ.
37*3a9fd824SRoger Pau Monné  * @arg == pointer to physdev_eoi structure.
38*3a9fd824SRoger Pau Monné  */
39*3a9fd824SRoger Pau Monné #define PHYSDEVOP_eoi                   12
40*3a9fd824SRoger Pau Monné struct physdev_eoi {
41*3a9fd824SRoger Pau Monné     /* IN */
42*3a9fd824SRoger Pau Monné     uint32_t irq;
43*3a9fd824SRoger Pau Monné };
44*3a9fd824SRoger Pau Monné typedef struct physdev_eoi physdev_eoi_t;
45*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_eoi_t);
46*3a9fd824SRoger Pau Monné 
47*3a9fd824SRoger Pau Monné /*
48*3a9fd824SRoger Pau Monné  * Register a shared page for the hypervisor to indicate whether the guest
49*3a9fd824SRoger Pau Monné  * must issue PHYSDEVOP_eoi. The semantics of PHYSDEVOP_eoi change slightly
50*3a9fd824SRoger Pau Monné  * once the guest used this function in that the associated event channel
51*3a9fd824SRoger Pau Monné  * will automatically get unmasked. The page registered is used as a bit
52*3a9fd824SRoger Pau Monné  * array indexed by Xen's PIRQ value.
53*3a9fd824SRoger Pau Monné  */
54*3a9fd824SRoger Pau Monné #define PHYSDEVOP_pirq_eoi_gmfn_v1       17
55*3a9fd824SRoger Pau Monné /*
56*3a9fd824SRoger Pau Monné  * Register a shared page for the hypervisor to indicate whether the
57*3a9fd824SRoger Pau Monné  * guest must issue PHYSDEVOP_eoi. This hypercall is very similar to
58*3a9fd824SRoger Pau Monné  * PHYSDEVOP_pirq_eoi_gmfn_v1 but it doesn't change the semantics of
59*3a9fd824SRoger Pau Monné  * PHYSDEVOP_eoi. The page registered is used as a bit array indexed by
60*3a9fd824SRoger Pau Monné  * Xen's PIRQ value.
61*3a9fd824SRoger Pau Monné  */
62*3a9fd824SRoger Pau Monné #define PHYSDEVOP_pirq_eoi_gmfn_v2       28
63*3a9fd824SRoger Pau Monné struct physdev_pirq_eoi_gmfn {
64*3a9fd824SRoger Pau Monné     /* IN */
65*3a9fd824SRoger Pau Monné     xen_pfn_t gmfn;
66*3a9fd824SRoger Pau Monné };
67*3a9fd824SRoger Pau Monné typedef struct physdev_pirq_eoi_gmfn physdev_pirq_eoi_gmfn_t;
68*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_pirq_eoi_gmfn_t);
69*3a9fd824SRoger Pau Monné 
70*3a9fd824SRoger Pau Monné /*
71*3a9fd824SRoger Pau Monné  * Query the status of an IRQ line.
72*3a9fd824SRoger Pau Monné  * @arg == pointer to physdev_irq_status_query structure.
73*3a9fd824SRoger Pau Monné  */
74*3a9fd824SRoger Pau Monné #define PHYSDEVOP_irq_status_query       5
75*3a9fd824SRoger Pau Monné struct physdev_irq_status_query {
76*3a9fd824SRoger Pau Monné     /* IN */
77*3a9fd824SRoger Pau Monné     uint32_t irq;
78*3a9fd824SRoger Pau Monné     /* OUT */
79*3a9fd824SRoger Pau Monné     uint32_t flags; /* XENIRQSTAT_* */
80*3a9fd824SRoger Pau Monné };
81*3a9fd824SRoger Pau Monné typedef struct physdev_irq_status_query physdev_irq_status_query_t;
82*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_irq_status_query_t);
83*3a9fd824SRoger Pau Monné 
84*3a9fd824SRoger Pau Monné /* Need to call PHYSDEVOP_eoi when the IRQ has been serviced? */
85*3a9fd824SRoger Pau Monné #define _XENIRQSTAT_needs_eoi   (0)
86*3a9fd824SRoger Pau Monné #define  XENIRQSTAT_needs_eoi   (1U<<_XENIRQSTAT_needs_eoi)
87*3a9fd824SRoger Pau Monné 
88*3a9fd824SRoger Pau Monné /* IRQ shared by multiple guests? */
89*3a9fd824SRoger Pau Monné #define _XENIRQSTAT_shared      (1)
90*3a9fd824SRoger Pau Monné #define  XENIRQSTAT_shared      (1U<<_XENIRQSTAT_shared)
91*3a9fd824SRoger Pau Monné 
92*3a9fd824SRoger Pau Monné /*
93*3a9fd824SRoger Pau Monné  * Set the current VCPU's I/O privilege level.
94*3a9fd824SRoger Pau Monné  * @arg == pointer to physdev_set_iopl structure.
95*3a9fd824SRoger Pau Monné  */
96*3a9fd824SRoger Pau Monné #define PHYSDEVOP_set_iopl               6
97*3a9fd824SRoger Pau Monné struct physdev_set_iopl {
98*3a9fd824SRoger Pau Monné     /* IN */
99*3a9fd824SRoger Pau Monné     uint32_t iopl;
100*3a9fd824SRoger Pau Monné };
101*3a9fd824SRoger Pau Monné typedef struct physdev_set_iopl physdev_set_iopl_t;
102*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_set_iopl_t);
103*3a9fd824SRoger Pau Monné 
104*3a9fd824SRoger Pau Monné /*
105*3a9fd824SRoger Pau Monné  * Set the current VCPU's I/O-port permissions bitmap.
106*3a9fd824SRoger Pau Monné  * @arg == pointer to physdev_set_iobitmap structure.
107*3a9fd824SRoger Pau Monné  */
108*3a9fd824SRoger Pau Monné #define PHYSDEVOP_set_iobitmap           7
109*3a9fd824SRoger Pau Monné struct physdev_set_iobitmap {
110*3a9fd824SRoger Pau Monné     /* IN */
111*3a9fd824SRoger Pau Monné #if __XEN_INTERFACE_VERSION__ >= 0x00030205
112*3a9fd824SRoger Pau Monné     XEN_GUEST_HANDLE(uint8) bitmap;
113*3a9fd824SRoger Pau Monné #else
114*3a9fd824SRoger Pau Monné     uint8_t *bitmap;
115*3a9fd824SRoger Pau Monné #endif
116*3a9fd824SRoger Pau Monné     uint32_t nr_ports;
117*3a9fd824SRoger Pau Monné };
118*3a9fd824SRoger Pau Monné typedef struct physdev_set_iobitmap physdev_set_iobitmap_t;
119*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_set_iobitmap_t);
120*3a9fd824SRoger Pau Monné 
121*3a9fd824SRoger Pau Monné /*
122*3a9fd824SRoger Pau Monné  * Read or write an IO-APIC register.
123*3a9fd824SRoger Pau Monné  * @arg == pointer to physdev_apic structure.
124*3a9fd824SRoger Pau Monné  */
125*3a9fd824SRoger Pau Monné #define PHYSDEVOP_apic_read              8
126*3a9fd824SRoger Pau Monné #define PHYSDEVOP_apic_write             9
127*3a9fd824SRoger Pau Monné struct physdev_apic {
128*3a9fd824SRoger Pau Monné     /* IN */
129*3a9fd824SRoger Pau Monné     unsigned long apic_physbase;
130*3a9fd824SRoger Pau Monné     uint32_t reg;
131*3a9fd824SRoger Pau Monné     /* IN or OUT */
132*3a9fd824SRoger Pau Monné     uint32_t value;
133*3a9fd824SRoger Pau Monné };
134*3a9fd824SRoger Pau Monné typedef struct physdev_apic physdev_apic_t;
135*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_apic_t);
136*3a9fd824SRoger Pau Monné 
137*3a9fd824SRoger Pau Monné /*
138*3a9fd824SRoger Pau Monné  * Allocate or free a physical upcall vector for the specified IRQ line.
139*3a9fd824SRoger Pau Monné  * @arg == pointer to physdev_irq structure.
140*3a9fd824SRoger Pau Monné  */
141*3a9fd824SRoger Pau Monné #define PHYSDEVOP_alloc_irq_vector      10
142*3a9fd824SRoger Pau Monné #define PHYSDEVOP_free_irq_vector       11
143*3a9fd824SRoger Pau Monné struct physdev_irq {
144*3a9fd824SRoger Pau Monné     /* IN */
145*3a9fd824SRoger Pau Monné     uint32_t irq;
146*3a9fd824SRoger Pau Monné     /* IN or OUT */
147*3a9fd824SRoger Pau Monné     uint32_t vector;
148*3a9fd824SRoger Pau Monné };
149*3a9fd824SRoger Pau Monné typedef struct physdev_irq physdev_irq_t;
150*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_irq_t);
151*3a9fd824SRoger Pau Monné 
152*3a9fd824SRoger Pau Monné #define MAP_PIRQ_TYPE_MSI               0x0
153*3a9fd824SRoger Pau Monné #define MAP_PIRQ_TYPE_GSI               0x1
154*3a9fd824SRoger Pau Monné #define MAP_PIRQ_TYPE_UNKNOWN           0x2
155*3a9fd824SRoger Pau Monné #define MAP_PIRQ_TYPE_MSI_SEG           0x3
156*3a9fd824SRoger Pau Monné #define MAP_PIRQ_TYPE_MULTI_MSI         0x4
157*3a9fd824SRoger Pau Monné 
158*3a9fd824SRoger Pau Monné #define PHYSDEVOP_map_pirq               13
159*3a9fd824SRoger Pau Monné struct physdev_map_pirq {
160*3a9fd824SRoger Pau Monné     domid_t domid;
161*3a9fd824SRoger Pau Monné     /* IN */
162*3a9fd824SRoger Pau Monné     int type;
163*3a9fd824SRoger Pau Monné     /* IN (ignored for ..._MULTI_MSI) */
164*3a9fd824SRoger Pau Monné     int index;
165*3a9fd824SRoger Pau Monné     /* IN or OUT */
166*3a9fd824SRoger Pau Monné     int pirq;
167*3a9fd824SRoger Pau Monné     /* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
168*3a9fd824SRoger Pau Monné     int bus;
169*3a9fd824SRoger Pau Monné     /* IN */
170*3a9fd824SRoger Pau Monné     int devfn;
171*3a9fd824SRoger Pau Monné     /* IN (also OUT for ..._MULTI_MSI) */
172*3a9fd824SRoger Pau Monné     int entry_nr;
173*3a9fd824SRoger Pau Monné     /* IN */
174*3a9fd824SRoger Pau Monné     uint64_t table_base;
175*3a9fd824SRoger Pau Monné };
176*3a9fd824SRoger Pau Monné typedef struct physdev_map_pirq physdev_map_pirq_t;
177*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_map_pirq_t);
178*3a9fd824SRoger Pau Monné 
179*3a9fd824SRoger Pau Monné #define PHYSDEVOP_unmap_pirq             14
180*3a9fd824SRoger Pau Monné struct physdev_unmap_pirq {
181*3a9fd824SRoger Pau Monné     domid_t domid;
182*3a9fd824SRoger Pau Monné     /* IN */
183*3a9fd824SRoger Pau Monné     int pirq;
184*3a9fd824SRoger Pau Monné };
185*3a9fd824SRoger Pau Monné 
186*3a9fd824SRoger Pau Monné typedef struct physdev_unmap_pirq physdev_unmap_pirq_t;
187*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_unmap_pirq_t);
188*3a9fd824SRoger Pau Monné 
189*3a9fd824SRoger Pau Monné #define PHYSDEVOP_manage_pci_add         15
190*3a9fd824SRoger Pau Monné #define PHYSDEVOP_manage_pci_remove      16
191*3a9fd824SRoger Pau Monné struct physdev_manage_pci {
192*3a9fd824SRoger Pau Monné     /* IN */
193*3a9fd824SRoger Pau Monné     uint8_t bus;
194*3a9fd824SRoger Pau Monné     uint8_t devfn;
195*3a9fd824SRoger Pau Monné };
196*3a9fd824SRoger Pau Monné 
197*3a9fd824SRoger Pau Monné typedef struct physdev_manage_pci physdev_manage_pci_t;
198*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_manage_pci_t);
199*3a9fd824SRoger Pau Monné 
200*3a9fd824SRoger Pau Monné #define PHYSDEVOP_restore_msi            19
201*3a9fd824SRoger Pau Monné struct physdev_restore_msi {
202*3a9fd824SRoger Pau Monné     /* IN */
203*3a9fd824SRoger Pau Monné     uint8_t bus;
204*3a9fd824SRoger Pau Monné     uint8_t devfn;
205*3a9fd824SRoger Pau Monné };
206*3a9fd824SRoger Pau Monné typedef struct physdev_restore_msi physdev_restore_msi_t;
207*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_restore_msi_t);
208*3a9fd824SRoger Pau Monné 
209*3a9fd824SRoger Pau Monné #define PHYSDEVOP_manage_pci_add_ext     20
210*3a9fd824SRoger Pau Monné struct physdev_manage_pci_ext {
211*3a9fd824SRoger Pau Monné     /* IN */
212*3a9fd824SRoger Pau Monné     uint8_t bus;
213*3a9fd824SRoger Pau Monné     uint8_t devfn;
214*3a9fd824SRoger Pau Monné     unsigned is_extfn;
215*3a9fd824SRoger Pau Monné     unsigned is_virtfn;
216*3a9fd824SRoger Pau Monné     struct {
217*3a9fd824SRoger Pau Monné         uint8_t bus;
218*3a9fd824SRoger Pau Monné         uint8_t devfn;
219*3a9fd824SRoger Pau Monné     } physfn;
220*3a9fd824SRoger Pau Monné };
221*3a9fd824SRoger Pau Monné 
222*3a9fd824SRoger Pau Monné typedef struct physdev_manage_pci_ext physdev_manage_pci_ext_t;
223*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_manage_pci_ext_t);
224*3a9fd824SRoger Pau Monné 
225*3a9fd824SRoger Pau Monné /*
226*3a9fd824SRoger Pau Monné  * Argument to physdev_op_compat() hypercall. Superceded by new physdev_op()
227*3a9fd824SRoger Pau Monné  * hypercall since 0x00030202.
228*3a9fd824SRoger Pau Monné  */
229*3a9fd824SRoger Pau Monné struct physdev_op {
230*3a9fd824SRoger Pau Monné     uint32_t cmd;
231*3a9fd824SRoger Pau Monné     union {
232*3a9fd824SRoger Pau Monné         physdev_irq_status_query_t irq_status_query;
233*3a9fd824SRoger Pau Monné         physdev_set_iopl_t         set_iopl;
234*3a9fd824SRoger Pau Monné         physdev_set_iobitmap_t     set_iobitmap;
235*3a9fd824SRoger Pau Monné         physdev_apic_t             apic_op;
236*3a9fd824SRoger Pau Monné         physdev_irq_t              irq_op;
237*3a9fd824SRoger Pau Monné     } u;
238*3a9fd824SRoger Pau Monné };
239*3a9fd824SRoger Pau Monné typedef struct physdev_op physdev_op_t;
240*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_op_t);
241*3a9fd824SRoger Pau Monné 
242*3a9fd824SRoger Pau Monné #define PHYSDEVOP_setup_gsi    21
243*3a9fd824SRoger Pau Monné struct physdev_setup_gsi {
244*3a9fd824SRoger Pau Monné     int gsi;
245*3a9fd824SRoger Pau Monné     /* IN */
246*3a9fd824SRoger Pau Monné     uint8_t triggering;
247*3a9fd824SRoger Pau Monné     /* IN */
248*3a9fd824SRoger Pau Monné     uint8_t polarity;
249*3a9fd824SRoger Pau Monné     /* IN */
250*3a9fd824SRoger Pau Monné };
251*3a9fd824SRoger Pau Monné 
252*3a9fd824SRoger Pau Monné typedef struct physdev_setup_gsi physdev_setup_gsi_t;
253*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_setup_gsi_t);
254*3a9fd824SRoger Pau Monné 
255*3a9fd824SRoger Pau Monné /* leave PHYSDEVOP 22 free */
256*3a9fd824SRoger Pau Monné 
257*3a9fd824SRoger Pau Monné /* type is MAP_PIRQ_TYPE_GSI or MAP_PIRQ_TYPE_MSI
258*3a9fd824SRoger Pau Monné  * the hypercall returns a free pirq */
259*3a9fd824SRoger Pau Monné #define PHYSDEVOP_get_free_pirq    23
260*3a9fd824SRoger Pau Monné struct physdev_get_free_pirq {
261*3a9fd824SRoger Pau Monné     /* IN */
262*3a9fd824SRoger Pau Monné     int type;
263*3a9fd824SRoger Pau Monné     /* OUT */
264*3a9fd824SRoger Pau Monné     uint32_t pirq;
265*3a9fd824SRoger Pau Monné };
266*3a9fd824SRoger Pau Monné 
267*3a9fd824SRoger Pau Monné typedef struct physdev_get_free_pirq physdev_get_free_pirq_t;
268*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_get_free_pirq_t);
269*3a9fd824SRoger Pau Monné 
270*3a9fd824SRoger Pau Monné #define XEN_PCI_MMCFG_RESERVED         0x1
271*3a9fd824SRoger Pau Monné 
272*3a9fd824SRoger Pau Monné #define PHYSDEVOP_pci_mmcfg_reserved    24
273*3a9fd824SRoger Pau Monné struct physdev_pci_mmcfg_reserved {
274*3a9fd824SRoger Pau Monné     uint64_t address;
275*3a9fd824SRoger Pau Monné     uint16_t segment;
276*3a9fd824SRoger Pau Monné     uint8_t start_bus;
277*3a9fd824SRoger Pau Monné     uint8_t end_bus;
278*3a9fd824SRoger Pau Monné     uint32_t flags;
279*3a9fd824SRoger Pau Monné };
280*3a9fd824SRoger Pau Monné typedef struct physdev_pci_mmcfg_reserved physdev_pci_mmcfg_reserved_t;
281*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_pci_mmcfg_reserved_t);
282*3a9fd824SRoger Pau Monné 
283*3a9fd824SRoger Pau Monné #define XEN_PCI_DEV_EXTFN              0x1
284*3a9fd824SRoger Pau Monné #define XEN_PCI_DEV_VIRTFN             0x2
285*3a9fd824SRoger Pau Monné #define XEN_PCI_DEV_PXM                0x4
286*3a9fd824SRoger Pau Monné 
287*3a9fd824SRoger Pau Monné #define PHYSDEVOP_pci_device_add        25
288*3a9fd824SRoger Pau Monné struct physdev_pci_device_add {
289*3a9fd824SRoger Pau Monné     /* IN */
290*3a9fd824SRoger Pau Monné     uint16_t seg;
291*3a9fd824SRoger Pau Monné     uint8_t bus;
292*3a9fd824SRoger Pau Monné     uint8_t devfn;
293*3a9fd824SRoger Pau Monné     uint32_t flags;
294*3a9fd824SRoger Pau Monné     struct {
295*3a9fd824SRoger Pau Monné         uint8_t bus;
296*3a9fd824SRoger Pau Monné         uint8_t devfn;
297*3a9fd824SRoger Pau Monné     } physfn;
298*3a9fd824SRoger Pau Monné     /*
299*3a9fd824SRoger Pau Monné      * Optional parameters array.
300*3a9fd824SRoger Pau Monné      * First element ([0]) is PXM domain associated with the device (if
301*3a9fd824SRoger Pau Monné      * XEN_PCI_DEV_PXM is set)
302*3a9fd824SRoger Pau Monné      */
303*3a9fd824SRoger Pau Monné     uint32_t optarr[XEN_FLEX_ARRAY_DIM];
304*3a9fd824SRoger Pau Monné };
305*3a9fd824SRoger Pau Monné typedef struct physdev_pci_device_add physdev_pci_device_add_t;
306*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_pci_device_add_t);
307*3a9fd824SRoger Pau Monné 
308*3a9fd824SRoger Pau Monné #define PHYSDEVOP_pci_device_remove     26
309*3a9fd824SRoger Pau Monné #define PHYSDEVOP_restore_msi_ext       27
310*3a9fd824SRoger Pau Monné /*
311*3a9fd824SRoger Pau Monné  * Dom0 should use these two to announce MMIO resources assigned to
312*3a9fd824SRoger Pau Monné  * MSI-X capable devices won't (prepare) or may (release) change.
313*3a9fd824SRoger Pau Monné  */
314*3a9fd824SRoger Pau Monné #define PHYSDEVOP_prepare_msix          30
315*3a9fd824SRoger Pau Monné #define PHYSDEVOP_release_msix          31
316*3a9fd824SRoger Pau Monné struct physdev_pci_device {
317*3a9fd824SRoger Pau Monné     /* IN */
318*3a9fd824SRoger Pau Monné     uint16_t seg;
319*3a9fd824SRoger Pau Monné     uint8_t bus;
320*3a9fd824SRoger Pau Monné     uint8_t devfn;
321*3a9fd824SRoger Pau Monné };
322*3a9fd824SRoger Pau Monné typedef struct physdev_pci_device physdev_pci_device_t;
323*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_pci_device_t);
324*3a9fd824SRoger Pau Monné 
325*3a9fd824SRoger Pau Monné #define PHYSDEVOP_DBGP_RESET_PREPARE    1
326*3a9fd824SRoger Pau Monné #define PHYSDEVOP_DBGP_RESET_DONE       2
327*3a9fd824SRoger Pau Monné 
328*3a9fd824SRoger Pau Monné #define PHYSDEVOP_DBGP_BUS_UNKNOWN      0
329*3a9fd824SRoger Pau Monné #define PHYSDEVOP_DBGP_BUS_PCI          1
330*3a9fd824SRoger Pau Monné 
331*3a9fd824SRoger Pau Monné #define PHYSDEVOP_dbgp_op               29
332*3a9fd824SRoger Pau Monné struct physdev_dbgp_op {
333*3a9fd824SRoger Pau Monné     /* IN */
334*3a9fd824SRoger Pau Monné     uint8_t op;
335*3a9fd824SRoger Pau Monné     uint8_t bus;
336*3a9fd824SRoger Pau Monné     union {
337*3a9fd824SRoger Pau Monné         physdev_pci_device_t pci;
338*3a9fd824SRoger Pau Monné     } u;
339*3a9fd824SRoger Pau Monné };
340*3a9fd824SRoger Pau Monné typedef struct physdev_dbgp_op physdev_dbgp_op_t;
341*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(physdev_dbgp_op_t);
342*3a9fd824SRoger Pau Monné 
343*3a9fd824SRoger Pau Monné /*
344*3a9fd824SRoger Pau Monné  * Notify that some PIRQ-bound event channels have been unmasked.
345*3a9fd824SRoger Pau Monné  * ** This command is obsolete since interface version 0x00030202 and is **
346*3a9fd824SRoger Pau Monné  * ** unsupported by newer versions of Xen.                              **
347*3a9fd824SRoger Pau Monné  */
348*3a9fd824SRoger Pau Monné #define PHYSDEVOP_IRQ_UNMASK_NOTIFY      4
349*3a9fd824SRoger Pau Monné 
350*3a9fd824SRoger Pau Monné #if __XEN_INTERFACE_VERSION__ < 0x00040600
351*3a9fd824SRoger Pau Monné /*
352*3a9fd824SRoger Pau Monné  * These all-capitals physdev operation names are superceded by the new names
353*3a9fd824SRoger Pau Monné  * (defined above) since interface version 0x00030202. The guard above was
354*3a9fd824SRoger Pau Monné  * added post-4.5 only though and hence shouldn't check for 0x00030202.
355*3a9fd824SRoger Pau Monné  */
356*3a9fd824SRoger Pau Monné #define PHYSDEVOP_IRQ_STATUS_QUERY       PHYSDEVOP_irq_status_query
357*3a9fd824SRoger Pau Monné #define PHYSDEVOP_SET_IOPL               PHYSDEVOP_set_iopl
358*3a9fd824SRoger Pau Monné #define PHYSDEVOP_SET_IOBITMAP           PHYSDEVOP_set_iobitmap
359*3a9fd824SRoger Pau Monné #define PHYSDEVOP_APIC_READ              PHYSDEVOP_apic_read
360*3a9fd824SRoger Pau Monné #define PHYSDEVOP_APIC_WRITE             PHYSDEVOP_apic_write
361*3a9fd824SRoger Pau Monné #define PHYSDEVOP_ASSIGN_VECTOR          PHYSDEVOP_alloc_irq_vector
362*3a9fd824SRoger Pau Monné #define PHYSDEVOP_FREE_VECTOR            PHYSDEVOP_free_irq_vector
363*3a9fd824SRoger Pau Monné #define PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY XENIRQSTAT_needs_eoi
364*3a9fd824SRoger Pau Monné #define PHYSDEVOP_IRQ_SHARED             XENIRQSTAT_shared
365*3a9fd824SRoger Pau Monné #endif
366*3a9fd824SRoger Pau Monné 
367*3a9fd824SRoger Pau Monné #if __XEN_INTERFACE_VERSION__ < 0x00040200
368*3a9fd824SRoger Pau Monné #define PHYSDEVOP_pirq_eoi_gmfn PHYSDEVOP_pirq_eoi_gmfn_v1
369*3a9fd824SRoger Pau Monné #else
370*3a9fd824SRoger Pau Monné #define PHYSDEVOP_pirq_eoi_gmfn PHYSDEVOP_pirq_eoi_gmfn_v2
371*3a9fd824SRoger Pau Monné #endif
372*3a9fd824SRoger Pau Monné 
373*3a9fd824SRoger Pau Monné #endif /* __XEN_PUBLIC_PHYSDEV_H__ */
374*3a9fd824SRoger Pau Monné 
375*3a9fd824SRoger Pau Monné /*
376*3a9fd824SRoger Pau Monné  * Local variables:
377*3a9fd824SRoger Pau Monné  * mode: C
378*3a9fd824SRoger Pau Monné  * c-file-style: "BSD"
379*3a9fd824SRoger Pau Monné  * c-basic-offset: 4
380*3a9fd824SRoger Pau Monné  * tab-width: 4
381*3a9fd824SRoger Pau Monné  * indent-tabs-mode: nil
382*3a9fd824SRoger Pau Monné  * End:
383*3a9fd824SRoger Pau Monné  */
384