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/linux/Documentation/devicetree/bindings/cache/
H A Dqcom,llcc.yaml4 $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
23 - qcom,ipq5424-llcc
24 - qcom,kaanapali-llcc
25 - qcom,qcs615-llcc
26 - qcom,qcs8300-llcc
27 - qcom,qdu1000-llcc
28 - qcom,sa8775p-llcc
29 - qcom,sar1130p-llcc
30 - qcom,sar2130p-llcc
[all …]
/linux/include/linux/soc/qcom/
H A Dllcc-qcom.h88 * @slice_id: llcc slice id
89 * @slice_size: Size allocated for the llcc slice
97 * struct llcc_edac_reg_data - llcc edac registers data for each error type
115 /* LLCC TRP registers */
125 /* LLCC Common registers */
130 /* LLCC DRP registers */
143 * struct llcc_drv_data - Data associated with the llcc driver
144 * @regmaps: regmaps associated with the llcc device
145 * @bcast_regmap: regmap associated with llcc broadcast OR offset
146 * @bcast_and_regmap: regmap associated with llcc broadcast AND offset
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8998-bwmon.yaml20 (DDR) - called LLCC BWMON.
38 - qcom,sm6350-llcc-bwmon
47 - qcom,qcs615-llcc-bwmon
48 - qcom,qcs8300-llcc-bwmon
49 - qcom,sa8775p-llcc-bwmon
50 - qcom,sc7180-llcc-bwmon
51 - qcom,sc8280xp-llcc-bwmon
53 - qcom,sm8250-llcc-bwmon
54 - qcom,sm8550-llcc-bwmon
55 - qcom,sm8650-llcc-bwmon
[all …]
/linux/drivers/edac/
H A Dqcom_edac.c12 #include <linux/soc/qcom/llcc-qcom.h>
265 "LLCC Data RAM correctable Error"); in dump_syn_reg()
269 "LLCC Data RAM uncorrectable Error"); in dump_syn_reg()
273 "LLCC Tag RAM correctable Error"); in dump_syn_reg()
277 "LLCC Tag RAM uncorrectable Error"); in dump_syn_reg()
352 edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank", in qcom_llcc_edac_probe()
362 edev_ctl->ctl_name = "llcc"; in qcom_llcc_edac_probe()
365 /* Check if LLCC driver has passed ECC IRQ */ in qcom_llcc_edac_probe()
/linux/drivers/soc/qcom/
H A Dllcc-qcom.c21 #include <linux/soc/qcom/llcc-qcom.h>
81 * struct llcc_slice_config - Data associated with the llcc slice
83 * @slice_id: llcc slice id for each client
97 * When configured to 0 all ways in llcc are probed.
3762 /* LLCC Common registers */
3767 /* LLCC DRP registers */
3789 /* LLCC Common registers */
3794 /* LLCC DRP registers */
3816 /* LLCC Common registers */
3821 /* LLCC DRP registers */
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_crtc.h194 * @bw_split_vote : true if bw controlled by llcc/dram bw properties
H A Ddpu_hw_catalog.h648 * @min_llcc_ib minimum llcc ib vote in kbps
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm850-samsung-w737.dts394 &llcc {
H A Dtalos.dtsi3578 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3688 llcc: system-cache-controller@9200000 { label
3689 compatible = "qcom,qcs615-llcc";
H A Dsm6350.dtsi1865 compatible = "qcom,sm6350-llcc";
1885 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1924 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
H A Dmonaco.dtsi4456 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4565 llcc: system-cache-controller@9200000 { label
4566 compatible = "qcom,qcs8300-llcc";
H A Dipq5424.dtsi444 compatible = "qcom,ipq5424-llcc";
H A Dsc7180.dtsi2976 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3029 compatible = "qcom,sc7180-llcc";
H A Dqdu1000.dtsi1601 compatible = "qcom,qdu1000-llcc";
H A Dsdm845.dtsi2226 llcc: system-cache-controller@1100000 { label
2227 compatible = "qcom,sdm845-llcc";
2243 compatible = "qcom,sdm845-llcc-bwmon";
H A Dsm8650.dtsi1848 llcc_lpi_mem: llcc-lpi@ff800000 {
7158 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
7259 compatible = "qcom,sm8650-llcc";
H A Dlemans.dtsi4207 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4301 llcc: system-cache-controller@9200000 { label
4302 compatible = "qcom,sa8775p-llcc";
H A Dsm8750.dtsi523 llcc_lpi_mem: llcc-lpi@ff800000 {
4041 compatible = "qcom,sm8750-llcc";
H A Dhamoa.dtsi696 llcc_lpi_mem: llcc-lpi@ff800000 {
8534 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
8657 compatible = "qcom,x1e80100-llcc";
H A Dsc8280xp.dtsi3839 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3930 compatible = "qcom,sc8280xp-llcc";
H A Dsm8250.dtsi4027 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4250 compatible = "qcom,sm8250-llcc";
H A Dsm8550.dtsi5459 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5554 compatible = "qcom,sm8550-llcc";
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c15 #include <linux/soc/qcom/llcc-qcom.h>
2117 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ in a6xx_llc_slices_destroy()
2130 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ in a6xx_llc_slices_init()
H A Da8xx_gpu.c15 #include <linux/soc/qcom/llcc-qcom.h>
/linux/drivers/net/ethernet/sun/
H A Dcassini.h2200 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
2298 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
2378 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2434 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,

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