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/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	pipeline.json	63 "PublicDescription": "This event counts valid cycles of L1D cache pipeline#0.", 66 "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." 69 "PublicDescription": "This event counts valid cycles of L1D cache pipeline#1.", 72 "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." 75 …"PublicDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagge… 78 …"BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged… 81 …"PublicDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagge… 84 …"BriefDescription": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged… 87 …"PublicDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagge… 90 …"BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged… [all …]
H A D	other.json	33 …because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and… 36 …because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and… 39 …mitted because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and… 42 …mitted because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and… 147 …"PublicDescription": "This event counts streaming prefetch requests to L1D cache generated by hard… 150 …"BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardw… 153 …"PublicDescription": "This event counts allocation type prefetch injection requests to L1D cache g… 156 …"BriefDescription": "This event counts allocation type prefetch injection requests to L1D cache ge… 159 …"PublicDescription": "This event counts non-allocation type prefetch injection requests to L1D cac… 162 …"BriefDescription": "This event counts non-allocation type prefetch injection requests to L1D cach…
/linux/Documentation/admin-guide/hw-vuln/
H A D	l1tf.rst	97 share the L1 Data Cache (L1D) is important for this. As the flaw allows 98 only to attack data which is present in L1D, a malicious guest running 99 on one Hyperthread can attack the data which is brought into the L1D by 145 - L1D Flush mode: 148 'L1D vulnerable' L1D flushing is disabled 150 'L1D conditional cache flushes' L1D flush is conditionally enabled 152 'L1D cache flushes' L1D flush is unconditionally enabled 170 1. L1D flush on VMENTER 173 To make sure that a guest cannot attack data which is present in the L1D 174 the hypervisor flushes the L1D before entering the guest. [all …]
H A D	l1d_flush.rst	1 L1D Flushing 5 leaks from the Level 1 Data cache (L1D) the kernel provides an opt-in 6 mechanism to flush the L1D cache on context switch. 10 (snooping of) from the L1D cache. 34 When PR_SPEC_L1D_FLUSH is enabled for a task a flush of the L1D cache is 38 If the underlying CPU supports L1D flushing in hardware, the hardware 44 The kernel command line allows to control the L1D flush mitigations at boot 58 The mechanism does not mitigate L1D data leaks between tasks belonging to 66 NOTE : The opt-in of a task for L1D flushing works only when the task's 68 requested L1D flushing is scheduled on a SMT-enabled core the kernel sends
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A D	pipeline.json	90 "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." 95 "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." 100 "BriefDescription": "This event counts valid cycles of L1D cache pipeline#2." 105 "BriefDescription": "This event counts completed requests in L1D cache pipeline#0." 110 "BriefDescription": "This event counts completed requests in L1D cache pipeline#1." 115 …"BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load in… 130 …"BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged… 135 …"BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged… 140 …"BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID i… 145 …"BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID i… [all …]
H A D	tlb.json	8 …"BriefDescription": "This event counts operations that cause a TLB refill of the L1D TLB. See L1D_… 12 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D TLB. See L1D_… 72 … "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 4KB page." 77 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 64KB page." 82 … "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 2MB page." 87 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 32MB page." 92 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 512MB page… 97 … "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 1GB page." 102 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 16GB page." 142 … "BriefDescription": "This event counts operations that cause a TLB refill of the L1D in 4KB page." [all …]
H A D	l1d_cache.json	4 …"BriefDescription": "This event counts operations that cause a refill of the L1D cache. See L1D_CA… 8 …"BriefDescription": "This event counts operations that cause a cache access to the L1D cache. See … 12 …"BriefDescription": "This event counts every write-back of data from the L1D cache. See L1D_CACHE_… 16 …"BriefDescription": "This event counts operations that cause a refill of the L1D cache that incurs… 20 "BriefDescription": "This event counts L1D CACHE caused by read access." 24 "BriefDescription": "This event counts L1D CACHE caused by write access."
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A D	extended.json	6 "BriefDescription": "L1D Read-only Exclusive Writes", 41 "BriefDescription": "L1D L2D Sourced Writes", 111 "BriefDescription": "L1D On-Chip L3 Sourced Writes", 118 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", 125 "BriefDescription": "L1D On-Node L4 Sourced Writes", 132 "BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention", 139 "BriefDescription": "L1D On-Node L3 Sourced Writes", 146 "BriefDescription": "L1D On-Drawer L4 Sourced Writes", 153 "BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention", 160 "BriefDescription": "L1D On-Drawer L3 Sourced Writes", [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A D	extended.json	6 "BriefDescription": "L1D Read-only Exclusive Writes", 41 "BriefDescription": "L1D L2D Sourced Writes", 111 "BriefDescription": "L1D On-Chip L3 Sourced Writes", 118 "BriefDescription": "L1D On-Chip Memory Sourced Writes", 125 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", 132 "BriefDescription": "L1D On-Cluster L3 Sourced Writes", 139 "BriefDescription": "L1D On-Cluster Memory Sourced Writes", 146 "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention", 153 "BriefDescription": "L1D Off-Cluster L3 Sourced Writes", 160 "BriefDescription": "L1D Off-Cluster Memory Sourced Writes", [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A D	extended.json	6 "BriefDescription": "L1D Read-only Exclusive Writes", 41 "BriefDescription": "L1D L2D Sourced Writes", 111 "BriefDescription": "L1D On-Chip L3 Sourced Writes", 118 "BriefDescription": "L1D On-Chip Memory Sourced Writes", 125 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", 132 "BriefDescription": "L1D On-Cluster L3 Sourced Writes", 139 "BriefDescription": "L1D On-Cluster Memory Sourced Writes", 146 "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention", 153 "BriefDescription": "L1D Off-Cluster L3 Sourced Writes", 160 "BriefDescription": "L1D Off-Cluster Memory Sourced Writes", [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	20 "BriefDescription": "L1D L2I Sourced Writes", 34 "BriefDescription": "L1D L2D Sourced Writes", 48 "BriefDescription": "L1D Local Memory Sourced Writes", 62 "BriefDescription": "L1D Read-only Exclusive Writes", 104 "BriefDescription": "L1D On-Chip L3 Sourced Writes", 111 "BriefDescription": "L1D Off-Chip L3 Sourced Writes", 118 "BriefDescription": "L1D Off-Book L3 Sourced Writes", 125 "BriefDescription": "L1D On-Book L4 Sourced Writes", 132 "BriefDescription": "L1D Off-Book L4 Sourced Writes", 146 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A D	extended.json	`6 "BriefDescription": "L1D L2 Sourced Writes", 41 "BriefDescription": "L1D Off-Book L3 Sourced Writes", 48 "BriefDescription": "L1D On-Book L4 Sourced Writes", 62 "BriefDescription": "L1D Read-only Exclusive Writes", 69 "BriefDescription": "L1D Off-Book L4 Sourced Writes", 90 "BriefDescription": "L1D Local Memory Sourced Writes", 146 "BriefDescription": "L1D On-Chip L3 Sourced Writes", 153 "BriefDescription": "L1D Off-Chip L3 Sourced Writes",`
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	cache.json	3 "BriefDescription": "L1D data line replacements", 6 "EventName": "L1D.REPLACEMENT", 7 "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 21 "BriefDescription": "L1D miss outstandings duration in cycles", 25 "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 30 "BriefDescription": "Cycles with L1D load Misses outstanding.", 35 "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", 41 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 116 "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardwar [all...]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	cache.json	6 "EventName": "L1D.REPLACEMENT", 7 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 12 "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 16 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 21 "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 27 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 32 "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 36 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 41 "BriefDescription": "Number of L1D misses that are outstanding", 45 "PublicDescription": "Counts number of L1D misse [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	cache.json	3 "BriefDescription": "L1D data line replacements", 6 "EventName": "L1D.REPLACEMENT", 7 "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 21 "BriefDescription": "L1D miss outstandings duration in cycles", 25 "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 30 "BriefDescription": "Cycles with L1D load Misses outstanding.", 35 "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", 41 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 116 "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardwar [all...]
/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A D	extended.json	`13 "BriefDescription": "L1D L2 Sourced Writes", 27 "BriefDescription": "L1D L3 Local Writes", 41 "BriefDescription": "L1D L3 Remote Writes", 48 "BriefDescription": "L1D Local Memory Sourced Writes", 62 "BriefDescription": "L1D Read-only Exclusive Writes",`
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	cache.json	3 "BriefDescription": "Allocated L1D data cache lines in M state.", 6 "EventName": "L1D.ALLOCATED_IN_M", 11 …"BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line rep… 14 "EventName": "L1D.ALL_M_REPLACEMENT", 19 "BriefDescription": "L1D data cache lines in M state evicted due to replacement.", 22 "EventName": "L1D.EVICTION", 27 "BriefDescription": "L1D data line replacements.", 30 "EventName": "L1D.REPLACEMENT", 31 …"PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new… 36 …"BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with oth… [all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	cache.json	3 "BriefDescription": "L1D data line replacements", 6 "EventName": "L1D.REPLACEMENT", 22 "BriefDescription": "L1D miss outstanding duration in cycles", 26 …"PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 a… 31 "BriefDescription": "Cycles with L1D load Misses outstanding.", 41 … "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", 46 … "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 51 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 59 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 63 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	cache.json	3 "BriefDescription": "L1D data line replacements", 6 "EventName": "L1D.REPLACEMENT", 22 "BriefDescription": "L1D miss outstanding duration in cycles", 26 …"PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 a… 31 "BriefDescription": "Cycles with L1D load Misses outstanding.", 41 … "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", 46 … "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 51 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 59 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 63 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", [all …]
/linux/arch/x86/kernel/cpu/
H A D	cacheinfo.c	155 union l1_cache l1i, l1d, *l1; in legacy_amd_cpuid4() local 163 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); in legacy_amd_cpuid4() 166 l1 = &l1d; in legacy_amd_cpuid4() 369 unsigned int l2, unsigned int l1i, unsigned int l1d) in intel_cacheinfo_done() argument 381 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : l1i + l1d); in intel_cacheinfo_done() 392 unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0; in intel_cacheinfo_0x2() local 404 case CACHE_L1_DATA: l1d += desc->c_size; break; in intel_cacheinfo_0x2() 410 intel_cacheinfo_done(c, l3, l2, l1i, l1d); in intel_cacheinfo_0x2() 427 unsigned int l1d = 0, l1i = 0, l2 = 0, l3 = 0; in intel_cacheinfo_0x4() local 453 l1d = id4.size / 1024; in intel_cacheinfo_0x4() [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	metrics.json	`33 "BriefDescription": "L1D cache read miss rate", 389 "BriefDescription": "L1D cache access - demand", 396 "BriefDescription": "L1D cache access - prefetch", 403 "BriefDescription": "L1D cache demand misses", 410 "BriefDescription": "L1D cache demand misses - read", 417 "BriefDescription": "L1D cache demand misses - write", 424 "BriefDescription": "L1D cache prefetch misses",`
/linux/arch/powerpc/include/asm/
H A D	cache.h	`54 struct ppc_cache_info l1d; member 64 return ppc64_caches.l1d.log_block_size; in l1_dcache_shift() 69 return ppc64_caches.l1d.block_size; in l1_dcache_bytes()`
/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A D	cache.json	`71 "BriefDescription": "L1D TLB access" 111 "BriefDescription": "L1D cache late miss" 117 "BriefDescription": "L1D cache prefetch"`
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	cache.json	6 "EventName": "L1D.REPLACEMENT", 7 …"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and … 12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav… 16 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (… 21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav… 27 …"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (… 32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res… 36 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack o… 41 "BriefDescription": "Number of L1D misses that are outstanding", 45 …L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) … [all …]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	cache.json	6 "EventName": "L1D.REPLACEMENT", 7 …"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and … 12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav… 16 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (… 21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav… 27 …"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (… 32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res… 36 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack o… 41 "BriefDescription": "Number of L1D misses that are outstanding", 45 …L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) … [all …]

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