xref: /linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1d_cache.json (revision f4f346c3465949ebba80c6cc52cd8d2eeaa545fd) 
1[
2    {
3        "ArchStdEvent": "L1D_CACHE_REFILL",
4        "BriefDescription": "This event counts operations that cause a refill of the L1D cache. See L1D_CACHE_REFILL of ARMv9 Reference Manual for more information."
5    },
6    {
7        "ArchStdEvent": "L1D_CACHE",
8        "BriefDescription": "This event counts operations that cause a cache access to the L1D cache. See L1D_CACHE of ARMv9 Reference Manual for more information."
9    },
10    {
11        "ArchStdEvent": "L1D_CACHE_WB",
12        "BriefDescription": "This event counts every write-back of data from the L1D cache. See L1D_CACHE_WB of ARMv9 Reference Manual for more information."
13    },
14    {
15        "ArchStdEvent": "L1D_CACHE_LMISS_RD",
16        "BriefDescription": "This event counts operations that cause a refill of the L1D cache that incurs additional latency."
17    },
18    {
19        "ArchStdEvent": "L1D_CACHE_RD",
20        "BriefDescription": "This event counts L1D CACHE caused by read access."
21    },
22    {
23        "ArchStdEvent": "L1D_CACHE_WR",
24        "BriefDescription": "This event counts L1D CACHE caused by write access."
25    },
26    {
27        "ArchStdEvent": "L1D_CACHE_REFILL_RD",
28        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by read access."
29    },
30    {
31        "ArchStdEvent": "L1D_CACHE_REFILL_WR",
32        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by write access."
33    },
34    {
35        "EventCode": "0x0200",
36        "EventName": "L1D_CACHE_DM",
37        "BriefDescription": "This event counts L1D_CACHE caused by demand access."
38    },
39    {
40        "EventCode": "0x0201",
41        "EventName": "L1D_CACHE_DM_RD",
42        "BriefDescription": "This event counts L1D_CACHE caused by demand read access."
43    },
44    {
45        "EventCode": "0x0202",
46        "EventName": "L1D_CACHE_DM_WR",
47        "BriefDescription": "This event counts L1D_CACHE caused by demand write access."
48    },
49    {
50        "EventCode": "0x0208",
51        "EventName": "L1D_CACHE_REFILL_DM",
52        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access."
53    },
54    {
55        "EventCode": "0x0209",
56        "EventName": "L1D_CACHE_REFILL_DM_RD",
57        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand read access."
58    },
59    {
60        "EventCode": "0x020A",
61        "EventName": "L1D_CACHE_REFILL_DM_WR",
62        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand write access."
63    },
64    {
65        "EventCode": "0x020D",
66        "EventName": "L1D_CACHE_BTC",
67        "BriefDescription": "This event counts demand access that hits cache line with shared status and requests exclusive access in the Level 1 data cache, causing a coherence access to outside of the Level 1 caches of this PE."
68    },
69    {
70        "ArchStdEvent": "L1D_CACHE_MISS",
71        "BriefDescription": "This event counts demand access that misses in the Level 1 data cache, causing an access to outside of the Level 1 caches of this PE."
72    },
73    {
74        "ArchStdEvent": "L1D_CACHE_HWPRF",
75        "BriefDescription": "This event counts L1D_CACHE caused by hardware prefetch."
76    },
77    {
78        "ArchStdEvent": "L1D_CACHE_REFILL_HWPRF",
79        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch."
80    },
81    {
82        "ArchStdEvent": "L1D_CACHE_HIT_RD",
83        "BriefDescription": "This event counts demand read counted by L1D_CACHE_RD that hits in the Level 1 data cache."
84    },
85    {
86        "ArchStdEvent": "L1D_CACHE_HIT_WR",
87        "BriefDescription": "This event counts demand write counted by L1D_CACHE_WR that hits in the Level 1 data cache."
88    },
89    {
90        "ArchStdEvent": "L1D_CACHE_HIT",
91        "BriefDescription": "This event counts access counted by L1D_CACHE that hits in the Level 1 data cache."
92    },
93    {
94        "ArchStdEvent": "L1D_LFB_HIT_RD",
95        "BriefDescription": "This event counts demand access counted by L1D_CACHE_HIT_RD that hits a cache line that is in the process of being loaded into the Level 1 data cache."
96    },
97    {
98        "ArchStdEvent": "L1D_LFB_HIT_WR",
99        "BriefDescription": "This event counts demand access counted by L1D_CACHE_HIT_WR that hits a cache line that is in the process of being loaded into the Level 1 data cache."
100    },
101    {
102        "ArchStdEvent": "L1D_CACHE_PRF",
103        "BriefDescription": "This event counts L1D_CACHE caused by hardware prefetch or software prefetch."
104    },
105    {
106        "ArchStdEvent": "L1D_CACHE_REFILL_PRF",
107        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch or software prefetch."
108    },
109    {
110        "ArchStdEvent": "L1D_CACHE_REFILL_PERCYC",
111        "BriefDescription": "This counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle."
112    }
113]
114